erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/pantherlake: Add new SoC config for Intel Wildcat Lake(WCL)

Browse source 
TEST=Compiled and Verified on Wildcat Lake Simulation Platform.

Change-Id: Ifd5bb19dd41c9e44b5399f570d4e21f03d5fce18
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87402
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Sowmya Aralguppe 2025-04-21 22:17:58 +05:30 • committed by Subrata Banik
commit 14b66cb01b
1 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/soc/intel/pantherlake/Kconfig
View file

@ -125,6 +125,12 @@ config SOC_INTEL_PANTHERLAKE_H
help
Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
config SOC_INTEL_WILDCATLAKE
bool
select SOC_INTEL_PANTHERLAKE_U_H
help
Choose this option if the mainboard is built using WCL system-on-a-chip (SoC).
if SOC_INTEL_PANTHERLAKE_BASE
config SOC_INTEL_PANTHERLAKE_TCSS_USB4_SUPPORT