erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/alderlake/vr_config: Add Amston Lake X7433RE

Browse source 
Add the Amston Lake (9W) with MCH_ID 0x4674 to the vr_config table.

Based on Intel docs 721616 rev 2.3.

BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor

Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87246
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Harrie Paijmans 2025-04-09 15:55:57 +02:00 • committed by Matt DeVillier
commit 432625d907
2 changed files with 20 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/alderlake/chip.h
View file

@ -83,6 +83,7 @@ enum soc_intel_alderlake_power_limits {
ADL_S_402_35W_CORE,
ADL_S_202_46W_CORE,
ADL_S_202_35W_CORE,
ASL_041_9W_CORE,
RPL_P_682_642_482_45W_CORE,
RPL_P_682_482_282_28W_CORE,
RPL_P_282_242_142_15W_CORE,
@ -185,6 +186,7 @@ static const struct {
{ PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W },
{ PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W },
{ PCI_DID_INTEL_ASL_ID_2, ASL_041_9W_CORE, TDP_9W },
{ PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W },
{ PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W },
{ PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W },

18
src/soc/intel/alderlake/vr_config.c
View file

@ -90,6 +90,20 @@
* +----------------+-----------+-------+-------+---------+-------------+----------+
*/
/*
* VR Configurations for IA and GT domains for ASL SKU's.
* Per doc#721616 ADL N ASL EDS Addendum
*
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
* | | |(mOhms)|(mOhms)| (A) | (A) | (msec) |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | ASL 041 (9W) | IA | 5.0 | 5.0 | 32 | 12 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
* | | GT | 6.5 | 6.5 | 29 | 22 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
*/
struct vr_lookup {
uint16_t mchid;
uint8_t tdp;
@ -134,6 +148,7 @@ static const struct vr_lookup vr_config_ll[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
@ -205,6 +220,7 @@ static const struct vr_lookup vr_config_icc[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_ICC(32, 29) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
@ -276,6 +292,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
@ -347,6 +364,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
{ PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 22) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },