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soc/intel/cnvi: Correct value of CNVI_ABORT_PLDR

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The definitions were reversed, as PCH_S should use 0x44, and all others
0x80.

These values can be seen in SlimBootloader, and most UEFI firmwares.

Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Sean Rhodes 2025-04-15 19:53:37 +01:00 • committed by Matt DeVillier
commit 360678f79a
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/common/block/include/intelblocks/cnvi.h
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@ -15,9 +15,9 @@
/* CNVi PLDR Control */
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#define CNVI_ABORT_PLDR 0x80
#else
#define CNVI_ABORT_PLDR 0x44
#else
#define CNVI_ABORT_PLDR 0x80
#endif
#define CNVI_ABORT_ENABLE BIT(0)