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soc/intel/ptl: Add Wildcat Lake platform reporting

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This commit updates the platform reporting logic to include support
for Wildcat Lake SoC.

Key changes:
  - Add Wildcat Lake-specific entries for MCH, PCH, and IGD device
    IDs.

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: Ia4efb173f3ff9247d50bcfa496ed92b211729a3a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87515
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Appukuttan V K 2025-05-02 15:32:20 +05:30 • committed by Matt DeVillier
commit f8071719e7
1 changed files with 36 additions and 0 deletions
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36
src/soc/intel/pantherlake/bootblock/report_platform.c
View file

@ -32,6 +32,8 @@ static struct {
{ PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" },
{ PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" },
{ PCI_DID_INTEL_PTL_H_ID_4, "Pantherlake H" },
{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
};
static struct {
@ -102,6 +104,38 @@ static struct {
{ PCI_DID_INTEL_PTL_H_ESPI_29, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_30, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_31, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_WCL_ESPI_0, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_1, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_2, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_3, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_4, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_5, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_6, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_7, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_8, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_9, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_10, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_11, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_12, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_13, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_14, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_15, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_16, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_17, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_18, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_19, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_20, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_21, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_22, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_23, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_24, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_25, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_26, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_27, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_28, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_29, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_30, "Wildcatlake SOC" },
{ PCI_DID_INTEL_WCL_ESPI_31, "Wildcatlake SOC" },
};
static struct {
@ -112,6 +146,8 @@ static struct {
{ PCI_DID_INTEL_PTL_H_GT2_1, "Pantherlake-H GT2" },
{ PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" },
{ PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" },
{ PCI_DID_INTEL_WCL_GT2_1, "Wildcatlake GT2" },
{ PCI_DID_INTEL_WCL_GT2_2, "Wildcatlake GT2" },
};
static inline uint8_t get_dev_revision(pci_devfn_t dev)