soc/intel/cannonlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>

src/mainboard/asrock/imb-1222/devicetree.cb

@@ -223,7 +223,6 @@ chip soc/intel/cannonlake
 			}"
 		end
 		device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieRpSlotImplemented[16]" = "1"
 			register "PcieClkSrcUsage[7]" = "16"
@@ -231,13 +230,11 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieClkSrcUsage[3]" = "4"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1)
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpSlotImplemented[5]" = "1"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
@@ -245,7 +242,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1)
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpSlotImplemented[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieClkSrcUsage[6]" = "6"

src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb

@@ -112,7 +112,6 @@ chip soc/intel/cannonlake
 		device ref uart2 on	end
 		device ref pcie_rp6 on
 			device pci 00.0 on end # x1 Card reader
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[3]" = "5"
 			register "PcieClkSrcClkReq[3]" = "3"
@@ -121,7 +120,6 @@ chip soc/intel/cannonlake
 			chip drivers/wifi/generic
 				device pci 00.0 on end
 			end
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -129,7 +127,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
@@ -137,7 +134,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -193,13 +193,11 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 9 for Card Reader
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	register "PcieClkSrcUsage[4]" = "8"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe port 13 for M.2 2280 SSD
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	register "PcieClkSrcUsage[2]" = "12"
 	register "PcieClkSrcClkReq[2]" = "2"

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -162,7 +162,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
 
 	# Enable Root port 9(x4) for NVMe.
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
@@ -170,7 +169,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 14 for M.2 E-key WLAN
-	register "PcieRpEnable[13]" = "true"
 	register "PcieRpLtrEnable[13]" = "true"
 	# RP 14 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "13"

src/mainboard/google/hatch/variants/helios/overridetree.cb

@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -176,6 +175,7 @@ chip soc/intel/cannonlake
 				device i2c 3b on end
 			end
 		end #I2C #4
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""

src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb

@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# Enable Root port 9(x2) for NVMe.
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
@@ -28,7 +27,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# Enable Root port 11(x2) for NVMe.
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# RP 11 uses CLK SRC 2
 	register "PcieClkSrcUsage[2]" = "10"
@@ -36,7 +34,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[2]" = "1"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
@@ -184,8 +181,9 @@ chip soc/intel/cannonlake
 				device i2c 3b on end
 			end
 		end #I2C #4
-		device ref pcie_rp9	on end # (x2 NVMe)
-		device ref pcie_rp11	on end # (x2 NVMe)
+		device ref pcie_rp9	on  end # (x2 NVMe)
+		device ref pcie_rp11	on  end # (x2 NVMe)
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""

src/mainboard/google/hatch/variants/kohaku/overridetree.cb

@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Enable DMIC1
 	register "PchHdaAudioLinkDmic1" = "1"
@@ -211,8 +210,7 @@ chip soc/intel/cannonlake
 				device i2c 0x1a on end
 			end
 		end
-		# No PCIe WiFi
-		device ref pcie_rp14	off end
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""

src/mainboard/google/hatch/variants/mushu/overridetree.cb

@@ -71,14 +71,12 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for M.2 E-key WLAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# RP 7 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "6"
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	# Enable Root port 13 (x4) for dGPU
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 5
 	register "PcieClkSrcUsage[5]" = "12"
@@ -178,6 +176,8 @@ chip soc/intel/cannonlake
 				device i2c 1a on end
 			end
 		end
+		device ref pcie_rp7	on  end
+		device ref pcie_rp13	on  end
 		device ref gspi1	on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""

src/mainboard/google/hatch/variants/nightfury/overridetree.cb

@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
 
 	# Enable DMIC1
 	register "PchHdaAudioLinkDmic1" = "1"
@@ -219,8 +218,7 @@ chip soc/intel/cannonlake
 				device i2c 0x39 on end
 			end
 		end
-		# No PCIe WiFi
-		device ref pcie_rp14	off end
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref emmc		on end
 		device ref hda		on
 			chip drivers/sof

src/mainboard/google/hatch/variants/palkia/overridetree.cb

@@ -22,9 +22,6 @@ chip soc/intel/cannonlake
 	register "usb2_ports[2]" = "USB2_PORT_LONG(OC_SKIP)"    # SD CARD
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD
 
-	# No PCIe WiFi
-	register "PcieRpEnable[13]" = "false"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field	     |	Value			 |
@@ -175,6 +172,7 @@ chip soc/intel/cannonlake
 				device i2c 39 on end
 			end
 		end
+		device ref pcie_rp14	off end # No PCIe Wifi
 		device ref hda		on
 			chip drivers/generic/max98357a
 				register "hid" = ""MX98357A""

src/mainboard/google/puff/variants/ambassador/overridetree.cb

@@ -184,10 +184,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/puff/variants/baseboard/devicetree.cb

@@ -162,7 +162,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
 
 	# Enable Root port 9(x4) for NVMe.
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
@@ -170,7 +169,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 14 for M.2 E-key WLAN
-	register "PcieRpEnable[13]" = "true"
 	register "PcieRpLtrEnable[13]" = "true"
 	# RP 14 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "13"

src/mainboard/google/puff/variants/dooly/overridetree.cb

@@ -173,7 +173,6 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/puff/variants/duffy/overridetree.cb

@@ -245,10 +245,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/puff/variants/faffy/overridetree.cb

@@ -253,10 +253,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/puff/variants/genesis/overridetree.cb

@@ -177,45 +177,38 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe root port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
 	register "PcieClkSrcClkReq[0]" = "0"
 
 	# PCIe root port 8 for WLAN
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	# Uses CLK SRC 5
 	register "PcieClkSrcUsage[5]" = "7"
 	register "PcieClkSrcClkReq[5]" = "5"
 
 	# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe root port 10 disabled
-	register "PcieRpEnable[9]" = "false"
 
 	# PCIe root port 11 TPU1
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[4]" = "10"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe root port 12 TPU0
-	register "PcieRpEnable[11]" = "true"
 	register "PcieRpLtrEnable[11]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[2]" = "11"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe port 13 for i350 NIC (x4)
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "12"
@@ -224,9 +217,6 @@ chip soc/intel/cannonlake
 	# effectively "not connected"
 	register "PcieClkSrcClkReq[3]" = "0xFF"
 	# Disable the remaining ports 14-16
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
 
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "vSD3_CD_B"
@@ -440,9 +430,6 @@ chip soc/intel/cannonlake
 			# X4 i350 NIC
 			register "PcieRpSlotImplemented[12]" = "0" # Built-in
 		end
-		device ref pcie_rp14	on end # non-root
-		device ref pcie_rp15	on end # non-root
-		device ref pcie_rp16	on end # non-root
 	end
 
 	# VR Settings Configuration for 4 Domains

src/mainboard/google/puff/variants/kaisa/overridetree.cb

@@ -245,10 +245,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/puff/variants/moonbuggy/overridetree.cb

@@ -177,45 +177,38 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe root port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
 	register "PcieClkSrcClkReq[0]" = "0"
 
 	# PCIe root port 8 for WLAN
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	# Uses CLK SRC 5
 	register "PcieClkSrcUsage[5]" = "7"
 	register "PcieClkSrcClkReq[5]" = "5"
 
 	# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe root port 10 disabled
-	register "PcieRpEnable[9]" = "false"
 
 	# PCIe root port 11 TPU1
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[4]" = "10"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe root port 12 TPU0
-	register "PcieRpEnable[11]" = "true"
 	register "PcieRpLtrEnable[11]" = "true"
 	# RP 11 uses CLK SRC 1
 	register "PcieClkSrcUsage[2]" = "11"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe port 13 for i350 NIC (x4)
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "12"
@@ -224,9 +217,6 @@ chip soc/intel/cannonlake
 	# effectively "not connected"
 	register "PcieClkSrcClkReq[3]" = "0xFF"
 	# Disable the remaining ports 14-16
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
 
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "vSD3_CD_B"
@@ -442,9 +432,6 @@ chip soc/intel/cannonlake
 			# X4 i350 NIC
 			register "PcieRpSlotImplemented[12]" = "0" # Built-in
 		end
-		device ref pcie_rp14	on end # non-root
-		device ref pcie_rp15	on end # non-root
-		device ref pcie_rp16	on end # non-root
 		device ref uart1	on end
 	end
 

src/mainboard/google/puff/variants/noibat/overridetree.cb

@@ -168,10 +168,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/puff/variants/puff/overridetree.cb

@@ -178,10 +178,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/puff/variants/scout/overridetree.cb

@@ -184,48 +184,37 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe root port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"
 	register "PcieClkSrcClkReq[0]" = "0"
 
 	# PCIe root port 8 for WLAN
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	# Uses CLK SRC 3
 	register "PcieClkSrcUsage[3]" = "7"
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	# PCIe root port 9 for SSD (PCIe Lanes 9-12)
-	register "PcieRpEnable[8]" = "true"
 	register "PcieRpLtrEnable[8]" = "true"
 	# RP 9 uses CLK SRC 1
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe root port 10-12 disabled
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
 
 	# PCIe root port 13 TPU0
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	# RP 13 uses CLK SRC 2
 	register "PcieClkSrcUsage[2]" = "12"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe root port 14 TPU1
-	register "PcieRpEnable[13]" = "true"
 	register "PcieRpLtrEnable[13]" = "true"
 	# RP 14 uses CLK SRC 4
 	register "PcieClkSrcUsage[4]" = "13"
 	register "PcieClkSrcClkReq[4]" = "4"
 
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "vSD3_CD_B"
 
@@ -422,8 +411,6 @@ chip soc/intel/cannonlake
 			# TPU1
 			register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot
 		end
-		device ref pcie_rp15	on end # non-root
-		device ref pcie_rp16	on end # non-root
 		device ref uart1	on end
 	end
 

src/mainboard/google/puff/variants/wyvern/overridetree.cb

@@ -179,10 +179,8 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 7 for LAN
-	register "PcieRpEnable[6]" = "true"
 	register "PcieRpLtrEnable[6]" = "true"
 	# PCIe port 11 (x2) for NVMe hybrid storage devices
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	# Uses CLK SRC 0
 	register "PcieClkSrcUsage[0]" = "6"

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -182,18 +182,15 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 10 for M.2 2230 WLAN
-	register "PcieRpEnable[9]" = "true"
 	register "PcieClkSrcUsage[2]" = "9"
 	register "PcieClkSrcClkReq[2]" = "2"
 
 	# PCIe port 11 for card reader
-	register "PcieRpEnable[10]" = "true"
 	register "PcieRpLtrEnable[10]" = "true"
 	register "PcieClkSrcUsage[1]" = "10"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 13 for M.2 2280 SSD
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	register "PcieClkSrcUsage[4]" = "12"
 	register "PcieClkSrcClkReq[4]" = "4"

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -182,23 +182,19 @@ chip soc/intel/cannonlake
 	}"
 
 	# PCIe port 8 for Card Reader
-	register "PcieRpEnable[7]" = "true"
 	register "PcieRpLtrEnable[7]" = "true"
 	register "PcieClkSrcUsage[4]" = "7"
 	register "PcieClkSrcClkReq[4]" = "4"
 
 	# PCIe port 9 for LAN
-	register "PcieRpEnable[8]" = "true"
 	register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	# PCIe port 10 for M.2 2230 WLAN
-	register "PcieRpEnable[9]" = "true"
 	register "PcieClkSrcUsage[1]" = "9"
 	register "PcieClkSrcClkReq[1]" = "1"
 
 	# PCIe port 13 for M.2 2280 SSD
-	register "PcieRpEnable[12]" = "true"
 	register "PcieRpLtrEnable[12]" = "true"
 	register "PcieClkSrcUsage[2]" = "12"
 	register "PcieClkSrcClkReq[2]" = "2"

src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb

@@ -42,31 +42,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "false"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "true"
-	register "PcieRpEnable[10]" = "true"
-	register "PcieRpEnable[11]" = "true"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-	register "PcieRpEnable[16]" = "false"
-	register "PcieRpEnable[17]" = "false"
-	register "PcieRpEnable[18]" = "false"
-	register "PcieRpEnable[19]" = "false"
-	register "PcieRpEnable[20]" = "false"
-	register "PcieRpEnable[21]" = "false"
-	register "PcieRpEnable[22]" = "false"
-	register "PcieRpEnable[23]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
@@ -95,30 +70,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1b.0 off end # PCI Express Port 17
-		device pci 1b.1 off end # PCI Express Port 18
-		device pci 1b.2 off end # PCI Express Port 19
-		device pci 1b.3 off end # PCI Express Port 20
-		device pci 1b.4 off end # PCI Express Port 21
-		device pci 1b.5 off end # PCI Express Port 22
-		device pci 1b.6 off end # PCI Express Port 23
-		device pci 1b.7 off end # PCI Express Port 24
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1

src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb

@@ -40,31 +40,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "false"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-	register "PcieRpEnable[16]" = "true"
-	register "PcieRpEnable[17]" = "true"
-	register "PcieRpEnable[18]" = "true"
-	register "PcieRpEnable[19]" = "true"
-	register "PcieRpEnable[20]" = "true"
-	register "PcieRpEnable[21]" = "true"
-	register "PcieRpEnable[22]" = "true"
-	register "PcieRpEnable[23]" = "true"
-
 	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -103,38 +78,28 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1
+		device ref pcie_rp1 on
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5
+		device ref pcie_rp5 on
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9 x4 SLOT 1
+		device ref pcie_rp9 on	# x4 SLOT 1
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1b.0 on	# PCI Express Port 17
+		device ref pcie_rp17 on
 			register "PcieRpSlotImplemented[16]" = "1"
 		end
-		device pci 1b.1 on	# PCI Express Port 18
+		device ref pcie_rp18 on
 			register "PcieRpSlotImplemented[17]" = "1"
 		end
-		device pci 1b.2 on	# PCI Express Port 19
+		device ref pcie_rp19 on
 			register "PcieRpSlotImplemented[18]" = "1"
 		end
-		device pci 1b.3 on	# PCI Express Port 20
+		device ref pcie_rp20 on
 			register "PcieRpSlotImplemented[19]" = "1"
 		end
-		device pci 1b.4 on	# PCI Express Port 21 X4 SLOT 2
+		device ref pcie_rp21 on	# x4 SLOT 2
 			register "PcieRpSlotImplemented[20]" = "1"
 		end
 		device pci 1e.1 off end # UART #1

src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb

@@ -3,23 +3,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -80,25 +63,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1

src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb

@@ -41,23 +41,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -92,25 +75,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.1 off end # UART #1
 		device pci 1f.6 on  end # GbE
 	end

src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb

@@ -26,23 +26,6 @@ chip soc/intel/cannonlake
 	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "true"
-	register "PcieRpEnable[1]" = "true"
-	register "PcieRpEnable[2]" = "true"
-	register "PcieRpEnable[3]" = "true"
-	register "PcieRpEnable[4]" = "true"
-	register "PcieRpEnable[5]" = "false"
-	register "PcieRpEnable[6]" = "false"
-	register "PcieRpEnable[7]" = "false"
-	register "PcieRpEnable[8]" = "true"
-	register "PcieRpEnable[9]" = "false"
-	register "PcieRpEnable[10]" = "false"
-	register "PcieRpEnable[11]" = "false"
-	register "PcieRpEnable[12]" = "false"
-	register "PcieRpEnable[13]" = "false"
-	register "PcieRpEnable[14]" = "false"
-	register "PcieRpEnable[15]" = "false"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -76,25 +59,15 @@ chip soc/intel/cannonlake
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on	# PCI Express Port 1 x4 SLOT1
+		device ref pcie_rp1 on	# x4 SLOT1
 			register "PcieRpSlotImplemented[0]" = "1"
 		end
-		device pci 1c.4 on	# PCI Express Port 5 x1 SLOT2/LAN
+		device ref pcie_rp5 on	# x1 SLOT2/LAN
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on	# PCI Express Port 9
+		device ref pcie_rp9 on
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.1 off end # UART #1
 		device pci 1f.6 on  end # GbE
 	end

src/mainboard/lenovo/m920q/devicetree.cb

@@ -67,28 +67,24 @@ chip soc/intel/cannonlake
 		end
 
 		device ref pcie_rp6	on # WLAN
-			register "PcieRpEnable[5]"		= "1"
 			register "PcieRpSlotImplemented[5]"	= "1"
 			register "PcieClkSrcUsage[3]"		= "5"
 			register "PcieClkSrcClkReq[3]"		= "3"
 		end
 
 		device ref pcie_rp9	on # PCIe x4
-			register "PcieRpEnable[8]"		= "1"
 			register "PcieRpSlotImplemented[8]"	= "1"
 			register "PcieClkSrcUsage[2]"		= "8"
 			register "PcieClkSrcClkReq[2]"		= "2"
 		end
 
 		device ref pcie_rp17 on # M.2 SSD #2
-			register "PcieRpEnable[16]"		= "1"
 			register "PcieRpSlotImplemented[16]"	= "1"
 			register "PcieClkSrcUsage[10]"		= "16"
 			register "PcieClkSrcClkReq[10]"		= "10"
 		end
 
 		device ref pcie_rp21 on # M.2 SSD #1
-			register "PcieRpEnable[20]"		= "1"
 			register "PcieRpSlotImplemented[20]"	= "1"
 			register "PcieClkSrcUsage[4]"		= "20"
 			register "PcieClkSrcClkReq[4]"		= "4"

src/mainboard/prodrive/hermes/devicetree.cb

@@ -171,7 +171,6 @@ chip soc/intel/cannonlake
 		device ref uart2 hidden end # in ACPI mode
 		device ref pcie_rp21 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieRpSlotImplemented[20]" = "1"
 			register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
@@ -180,7 +179,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp1 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieRpSlotImplemented[0]" = "1"
 			register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
@@ -188,28 +186,24 @@ chip soc/intel/cannonlake
 			register "PcieRpAspm[0]" = "AspmDisabled"
 		end
 		device ref pcie_rp5 on	# PHY 3
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 3
 			end
 		end
 		device ref pcie_rp6 on	# PHY 4
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 4
 			end
 		end
 		device ref pcie_rp7 on	# PHY 2
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpLtrEnable[6]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 2
 			end
 		end
 		device ref pcie_rp8 on	# PHY 1
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 1
@@ -217,12 +211,10 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieRpSlotImplemented[8]" = "1"
 		end
 		device ref pcie_rp14 on	# PHY 0
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			device pci 00.0 on
 				smbios_dev_info 0
@@ -232,13 +224,11 @@ chip soc/intel/cannonlake
 			device pci 00.0 on	# Aspeed PCI Bridge
 				device pci 00.0 on end  # Aspeed 2500 VGA
 			end
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieRpSlotImplemented[14]" = "1"
 		end
 		device ref pcie_rp16 on	# M.2 E/CNVi
 			# Disabled when CNVi is present
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieRpSlotImplemented[15]" = "1"
 		end

src/mainboard/protectli/vault_cml/devicetree.cb

@@ -52,15 +52,6 @@ chip soc/intel/cannonlake
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[2]" = "1"
 
-	register "PcieRpEnable[4]" = "true" # LAN1
-	register "PcieRpEnable[5]" = "true" # LAN2
-	register "PcieRpEnable[6]" = "true" # LAN3
-	register "PcieRpEnable[7]" = "true" # LAN4
-	register "PcieRpEnable[8]" = "true" # LAN5
-	register "PcieRpEnable[9]" = "true" # LAN6
-	register "PcieRpEnable[11]" = "true" # M.2 WiFi
-	register "PcieRpEnable[12]" = "true" # M.2 NVMe x4
-
 	# Enable Advanced Error Reporting for RP 5-10, 12, 13
 	register "PcieRpAdvancedErrorReporting[4]" = "1"
 	register "PcieRpAdvancedErrorReporting[5]" = "1"

src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb

@@ -125,7 +125,6 @@ chip soc/intel/cannonlake
 			register "SataPortsDevSlp[2]" = "1"
 		end
 		device ref pcie_rp7 on	# x1 M.2/E 2230 (WLAN)
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpSlotImplemented[6]" = "1"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieRpHotPlug[6]" = "1"
@@ -135,12 +134,10 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8 on
 			device pci 00.0 on end # x1 (LAN)
-			register "PcieRpEnable[7]" = "true"
 			register "PcieClkSrcUsage[3]" = "7"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp9 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpSlotImplemented[8]" = "1"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
@@ -148,7 +145,6 @@ chip soc/intel/cannonlake
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpSlotImplemented[12]" = "1"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"

src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb

@@ -118,7 +118,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8 on	# x1 M.2/E 2230 (WLAN)
 			register "PcieRpSlotImplemented[7]" = "1"
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
 			register "PcieClkSrcUsage[2]" = "0x80"
@@ -126,13 +125,11 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp10 on
 			device pci 00.0 on end # x1 (LAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieClkSrcUsage[3]" = "9"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
 			register "PcieRpSlotImplemented[12]" = "1"
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"
 			register "PcieClkSrcClkReq[1]" = "1"

src/mainboard/purism/librem_l1um_v2/devicetree.cb

@@ -210,20 +210,17 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp21 on
 			register "PcieRpSlotImplemented[20]" = "1"
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp1 on
 			register "PcieRpSlotImplemented[0]" = "1"
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x80"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9 on	# GbE #1
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[14]" = "8"
 			# Type indexes are needed for systemd to use "onboard" names by default
@@ -236,12 +233,10 @@ chip soc/intel/cannonlake
 			end
 		end
 		device ref pcie_rp10 on	# BMC video
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "true"
 			register "PcieClkSrcUsage[8]" = "9"
 		end
 		device ref pcie_rp11 on	# GbE #2
-			register "PcieRpEnable[10]" = "true"
 			register "PcieRpLtrEnable[10]" = "true"
 			register "PcieClkSrcUsage[11]" = "10"
 			device pci 00.0 on

src/mainboard/siemens/chili/variants/base/devicetree.cb

@@ -38,25 +38,21 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5		on
 			device pci 00.0 on end	# x1 i219
-			register "PcieRpEnable[4]" = "true"
 			register "PcieClkSrcUsage[4]" = "0x70"
 			register "PcieClkSrcClkReq[4]" = "4"
 			register "PcieRpSlotImplemented[4]" = "0"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# x1 i210
-			register "PcieRpEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
 			register "PcieRpSlotImplemented[5]" = "0"
 		end
 		device ref pcie_rp7		on
-			register "PcieRpEnable[6]" = "true"
 			register "PcieRpSlotImplemented[6]" = "1"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp17		on
-			register "PcieRpEnable[16]" = "true"
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
 			register "PcieRpSlotImplemented[16]" = "1"

src/mainboard/siemens/chili/variants/chili/devicetree.cb

@@ -81,39 +81,33 @@ chip soc/intel/cannonlake
 			end
 		end
 		device ref pcie_rp1		off
-			register "PcieRpEnable[0]" = "false" # Debug (x1)
 			register "PcieClkSrcUsage[2]" = "0"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp5		on
-			register "PcieRpEnable[4]" = "true" # CORE (x1)
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "4"
 			register "PcieRpSlotImplemented[4]" = "1"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# i210 (x1)
-			register "PcieRpEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
 			register "PcieRpSlotImplemented[5]" = "0"
 		end
 		device ref pcie_rp7		on
 			device pci 00.0 on end	# VL805 Front Rack/UIB (x1)
-			register "PcieRpEnable[6]" = "true"
 			register "PcieClkSrcUsage[1]" = "6"
 			register "PcieClkSrcClkReq[1]" = "1"
 			register "PcieRpSlotImplemented[6]" = "0"
 		end
 		device ref pcie_rp8		on
 			device pci 00.0 on end	# VL805 Back MB (x1)
-			register "PcieRpEnable[7]" = "true"
 			register "PcieClkSrcUsage[0]" = "7"
 			register "PcieClkSrcClkReq[0]" = "0"
 			register "PcieRpSlotImplemented[7]" = "0"
 		end
 		device ref pcie_rp17		on
-			register "PcieRpEnable[16]" = "true" # NVMe (x4)
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
 			register "PcieRpSlotImplemented[16]" = "1"

src/mainboard/starlabs/starbook/variants/cml/devicetree.cb

@@ -163,7 +163,6 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref pcie_rp9 on						# SSD x4
 			register "PcieRpSlotImplemented[8]"	= "1"
-			register "PcieRpEnable[8]"		= "1"
 			register "PcieRpLtrEnable[8]"		= "true"
 			register "PcieClkSrcUsage[1]"		= "0x08"
 			register "PcieClkSrcClkReq[1]"		= "1"

src/mainboard/system76/addw1/devicetree.cb

@@ -98,7 +98,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17	on
 			# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieRpHotPlug[16]" = "1"
 			register "PcieClkSrcUsage[0]" = "16"
@@ -106,7 +105,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 10 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			register "PcieClkSrcClkReq[10]" = "10"
@@ -114,7 +112,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 9 (SSD1)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
@@ -122,7 +119,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 5 (GLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[5]" = "13"
 			register "PcieClkSrcClkReq[5]" = "5"
@@ -130,7 +126,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 7 (Card Reader)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[7]" = "14"
 			register "PcieClkSrcClkReq[7]" = "7"
@@ -138,7 +133,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"

src/mainboard/system76/bonw14/devicetree.cb

@@ -113,21 +113,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17	on
 			# PCI Express root port #17 x4, Clock 14 (SSD2)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieClkSrcUsage[14]" = "16"
 			register "PcieClkSrcClkReq[14]" = "14"
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 15 (SSD3)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[15]" = "20"
 			register "PcieClkSrcClkReq[15]" = "15"
 		end
 		device ref pcie_rp1	on
 			# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
-			register "PcieRpEnable[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieRpHotPlug[0]" = "1"
 			register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
@@ -135,35 +132,30 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5	on
 			# PCI Express root port #5 x4, Clock 10 (USB 3.2)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieClkSrcUsage[10]" = "4"
 			register "PcieClkSrcClkReq[10]" = "10"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 8 (SSD)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[8]" = "8"
 			register "PcieClkSrcClkReq[8]" = "8"
 		end
 		device ref pcie_rp13	on
 			# PCI Express root port #13 x1, Clock 0 (WLAN)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[0]" = "12"
 			register "PcieClkSrcClkReq[0]" = "0"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 1 (GLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[1]" = "13"
 			register "PcieClkSrcClkReq[1]" = "1"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 4 (Card Reader)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[4]" = "14"
 			register "PcieClkSrcClkReq[4]" = "4"

src/mainboard/system76/cml-u/variants/darp6/overridetree.cb

@@ -40,7 +40,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[4]" = "4"
@@ -48,21 +47,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"

src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

@@ -33,7 +33,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[4]" = "4"
@@ -41,21 +40,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"

src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp6	on
 			device pci 00.0 on end # x1 Card reader
-			register "PcieRpEnable[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[3]" = "5"
 			register "PcieClkSrcClkReq[3]" = "3"
@@ -49,7 +48,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
-			register "PcieRpEnable[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -61,7 +59,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
@@ -70,7 +67,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp13	on
 			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"

src/mainboard/system76/gaze15/devicetree.cb

@@ -96,7 +96,6 @@ chip soc/intel/cannonlake
 		device ref uart2	on	end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
@@ -104,7 +103,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 10 (SSD)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
@@ -112,7 +110,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 6 (WLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[6]" = "13"
 			register "PcieClkSrcClkReq[6]" = "6"
@@ -120,7 +117,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 5 (LAN)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[5]" = "14"
 			register "PcieClkSrcClkReq[5]" = "5"

src/mainboard/system76/oryp5/devicetree.cb

@@ -109,35 +109,30 @@ chip soc/intel/cannonlake
 		device ref uart2	on	end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 12 (SSD)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 13 (WLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[13]" = "13"
 			register "PcieClkSrcClkReq[13]" = "13"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 14 (GLAN)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[14]" = "14"
 			register "PcieClkSrcClkReq[14]" = "14"
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 15 (Card Reader)
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[15]" = "15"
 			register "PcieClkSrcClkReq[15]" = "15"

src/mainboard/system76/oryp6/devicetree.cb

@@ -106,7 +106,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17	on
 			# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
-			register "PcieRpEnable[16]" = "true"
 			register "PcieRpLtrEnable[16]" = "true"
 			register "PcieRpHotPlug[16]" = "1"
 			register "PcieClkSrcUsage[0]" = "16"
@@ -115,7 +114,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
-			register "PcieRpEnable[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
@@ -123,7 +121,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express root port #9 x4, Clock 12 (SSD1)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
@@ -131,7 +128,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp14	on
 			# PCI Express root port #14 x1, Clock 7 (GLAN)
-			register "PcieRpEnable[13]" = "true"
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[7]" = "13"
 			register "PcieClkSrcClkReq[7]" = "7"
@@ -139,7 +135,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 9 (Card Reader)
-			register "PcieRpEnable[14]" = "true"
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[9]" = "14"
 			register "PcieClkSrcClkReq[9]" = "9"
@@ -147,7 +142,6 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
-			register "PcieRpEnable[15]" = "true"
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"

src/mainboard/system76/whl-u/devicetree.cb

@@ -99,7 +99,6 @@ chip soc/intel/cannonlake
 		device ref pcie_rp1	on	end
 		device ref pcie_rp5	on
 			# PCI Express Root port #5 x4, Clock 4 (TBT)
-			register "PcieRpEnable[4]" = "true"
 			register "PcieRpLtrEnable[4]" = "true"
 			register "PcieRpHotPlug[4]" = "1"
 			register "PcieClkSrcUsage[4]" = "4"
@@ -107,21 +106,18 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9	on
 			# PCI Express Root port #9 x1, Clock 3 (LAN)
-			register "PcieRpEnable[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10	on
 			# PCI Express Root port #10 x1, Clock 2 (WLAN)
-			register "PcieRpEnable[9]" = "true"
 			register "PcieRpLtrEnable[9]" = "false"
 			register "PcieClkSrcUsage[2]" = "9"
 			register "PcieClkSrcClkReq[2]" = "2"
 		end
 		device ref pcie_rp13	on
 			# PCI Express Root port #13 x4, Clock 5 (NVMe)
-			register "PcieRpEnable[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"

src/soc/intel/cannonlake/Makefile.mk

@@ -21,6 +21,7 @@ romstage-y += cnl_memcfg_init.c
 romstage-y += gspi.c
 romstage-y += i2c.c
 romstage-y += lpc.c
+romstage-y += pcie_rp.c
 romstage-y += pmutil.c
 romstage-y += reset.c
 romstage-y += spi.c
@@ -39,6 +40,7 @@ ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += nhlt.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += pmutil.c
 ramstage-y += reset.c

src/soc/intel/cannonlake/chip.c

@@ -15,23 +15,11 @@
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 
 #include "chip.h"
 
-static const struct pcie_rp_group pch_lp_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
-	{ 0 }
-};
-
-static const struct pcie_rp_group pch_h_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
-	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8, .lcap_port_base = 1 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
@@ -155,7 +143,7 @@ void soc_init_pre_device(void *chip_info)
 
 	/* swap enabled PCI ports in device tree if needed */
 	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) {
-		pcie_rp_update_devicetree(pch_h_rp_groups);
+		pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 
 		/*
 		 * Fix up device ID of hidden PCI device in devicetree.
@@ -166,7 +154,7 @@ void soc_init_pre_device(void *chip_info)
 			uart2->device = PCI_DID_INTEL_CNP_H_UART2;
 
 	} else {
-		pcie_rp_update_devicetree(pch_lp_rp_groups);
+		pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 	}
 }
 

src/soc/intel/cannonlake/chip.h

@@ -166,7 +166,6 @@ struct soc_intel_cannonlake_config {
 	bool PchHdaAudioLinkSndw4;
 
 	/* PCIe Root Ports */
-	bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */

src/soc/intel/cannonlake/include/soc/pcie.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_CANNONLAKE_PCIE_H__
+#define __SOC_CANNONLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void);
+
+#endif /* __SOC_CANNONLAKE_PCIE_H__ */

src/soc/intel/cannonlake/pcie_rp.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
+	{ 0 }
+};
+
+static const struct pcie_rp_group pch_h_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8, .lcap_port_base = 1 },
+	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8, .lcap_port_base = 1 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void)
+{
+	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
+		return pch_h_rp_groups;
+
+	return pch_lp_rp_groups;
+}

src/soc/intel/cannonlake/romstage/fsp_params.c

@@ -6,11 +6,13 @@
 #include <console/console.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/pcie_rp.h>
 #include <intelblocks/pmclib.h>
 #include <option.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <types.h>
 
@@ -24,7 +26,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
 	unsigned int i;
-	uint32_t mask = 0;
 
 	m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
 
@@ -51,11 +52,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 		m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
 	m_cfg->RMT = config->RMT;
 
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
 	m_cfg->PrmrrSize = get_valid_prmrr_size();
 	m_cfg->EnableC6Dram = config->enable_c6dram;
 #if CONFIG(SOC_INTEL_COMETLAKE)