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soc/intel/alderlake/vr_config: Add i7-1370PE

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Add the Raptorlake-P/H/H Refresh (6+8)(28W) with MCH_ID 0xa706
to the vr_config table.

BUG=NA
TEST=Customer platform with Raptorlake-P

Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87245
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Harrie Paijmans 2025-04-09 15:20:24 +02:00 • committed by Matt DeVillier
commit c8f7f67745
1 changed files with 5 additions and 1 deletions
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6
src/soc/intel/alderlake/vr_config.c
View file

@ -81,7 +81,7 @@
* | | GT | 3.2 | 3.2 | 55 | 86 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 33 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
* + 682(28W) +-----------+-------+-------+---------+-------------+----------+
* | | GT | 3.2 | 3.2 | 55 | 33 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 22 | 28000 |
@ -134,6 +134,7 @@ static const struct vr_lookup vr_config_ll[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
@ -204,6 +205,7 @@ static const struct vr_lookup vr_config_icc[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
@ -274,6 +276,7 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
@ -344,6 +347,7 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
{ PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
{ PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
{ PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },