Move BTRK to \_SB.PCI0 so that the CNVi driver can correctly
access it.
Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84990
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.
This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.
All data structures utilized by this function are updated accordingly.
BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.
Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move PCU specific code into separate files:
- PCUs registers are now locked by the PCI driver final call
- set_bios_init_completion() is not part of PCU1 driver
- Integrate config_reset_cpl3_csrs() into PCU driver
TEST: Still boots on ocp/tiogapass.
Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
FSP only configures the PCH IOAPIC. Let coreboot reconfigure all
IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the
IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI
address for each IOAPIC instead of assume it's a linear address space.
Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.
TEST: Booted on ocp/tiogapass with correct GSI bases asigned
matching the _PRT advertised GSI bases.
Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002
Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85170
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch corrects the calculation of the _ADR value for the Intel UFS
controller in the `soc/ufs.h` header file.
The previous calculation incorrectly included a hardcoded value (0x0007)
in the lower bits of the _ADR. This is not in line with the Panther Lake
EDS specification (doc: 815002)
BUG=b:382243957
TEST=Able to build and boot google/fatcat.
> iasl -d /sys/firmware/acpi/tables/DSDT
Device (UFS)
{
Name (_ADR, 0x00170000) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85528
Reviewed-by: Divagar Mohandass <divagar.mohandass@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
pcr_read16(PID_ITSS, itss_soc_get_on_chip_dev_pir(dev)) returns
the register content and should not be compared with
PCI_ITSS_PIR(0) which is an address offset. By now, we assume the
returned PIR is always effective and usable.
Change-Id: I2e61629bdcdea33f260bfbc47f22d40d9a869c6b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85284
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: <yuchi.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add const qualifer for itss_get_on_chip_dev_pirq and
itss_soc_get_on_chip_dev_pir so that these ops could be used for
both struct device * input and const struct device * input.
Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
If CHIPSET_LOCKDOWN_COREBOOT is selected, lpc_lockdown_config() will
be executed in common pch/lockdown firstly. Remove xeon_sp layer
lpc_lockdown_config() to avoid duplication.
The duplicated part are in src/soc/intel/common/pch/lockdown/lockdown.c:
static void platform_lockdown_config(void *unused)
{
int chipset_lockdown;
chipset_lockdown = get_lockdown_config();
/* SPI lock down configuration */
fast_spi_lockdown_cfg(chipset_lockdown);
/* LPC/eSPI lock down configuration */
lpc_lockdown_config(chipset_lockdown);
...
}
Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85286
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Drop function fast_spi_set_vcl as the same code already exists
as fast_spi_vscc0_lock() and is already run on xeon_sp.
Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
acpigen_write_PRT_pre_routed should support _PRT reporting for
both domains and PCI root ports.
TESTED=Build and boot on intel/avenuecity CRB
_PRT will be correctly reported and IRQ routing missing error in
dmesg will disappear
[ 40.406496] pcieport 0000:14:08.0: can't derive routing for PCI INT A
[ 40.413799] pci 0000:17:00.0: PCI INT A: no GSI
[ 40.418965] pcieport 0000:14:08.0: can't derive routing for PCI INT A
[ 40.426272] ast 0000:18:00.0: PCI INT A: no GSI
Change-Id: I07b9ce7b698a0bad30f0a20998a6543101d12542
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85151
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: <yuchi.chen@intel.com>
PCI devices not pre-routed will have their interrupt line left as
0. Skip these devices in _PRT reporting.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: I3d51b75eb0fd1c4ca877f6ac884de2742e7f9630
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85152
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: <yuchi.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch corrects the conditional inclusion of the `ufs.asl` file in
the southbridge ACPI configuration.
Previously, the inclusion of `ufs.asl` was incorrectly dependent on the
`MAINBOARD_USES_IFD_GBE_REGION` Kconfig option. This prevented the UFS
ACPI entry from being included in the DSDT when
`MAINBOARD_USES_IFD_GBE_REGION` was disabled, causing issues with
booting from UFS media.
This commit fixes the issue by ensuring that `ufs.asl` is included
based on the `SOC_INTEL_PANTHERLAKE_U_H` Kconfig option, which correctly
reflects the presence of UFS hardware.
This change ensures that the UFS ACPI device is correctly enumerated and
available to the operating system.
BUG=b:382243957
TEST=Able to verify UFS ACPI device is available inside DSDT table.
Change-Id: Ic8e87c57dd2db30f0ba13ac0a9f7fd2db877039a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
CPX uses the same PCH as SKX does, thus it has the same ACPI timer
timer and PM2 control fields as SKX.
Copy the code from skx to cpx to reduce code differences. Allows to
merge both codebases into one.
Change-Id: I92fc63a6655fb915b2c06273c3259dddfb93e8bb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the supported mainboards have a 8042 compatible chip,
thus drop it from the common code.
When such board is added it can update fadt->iapc_boot_arch
by installing a mainboard_fill_fadt() method.
Change-Id: I40cafcec57dd49399ce449700c81a1f27c1ded99
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85507
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both CPX and SKX always enable EIST, thus the generic
generate_p_state_entries() method can be used to generate _PSS.
This also reduces code differences between skx and cpx and allows
to merge both codebases into one.
Change-Id: Ic7b03eef9498f2c442745119b24fb8b5c6169a08
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Do not use a define for a PCI register to lock a MSR.
The defines will be moved in the following commit to it's own header,
preventing the use in CPX CPU init.
Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move CPU init closer to other SoC and CPX.
FSP-S only is aware of socket 0, thus all cores must rerun all
settings already done by FSP, in order to set up socket 1 as well.
FSP sets the following on socket0:
- Set BIT20 in MSR_VR_MISC_CONFIG
- Set LTR_IIO_DISABLE in MSR_POWER_CTL
Lock the following MSRs:
- MSR_SNC_CONFIG
- MSR_CONFIG_TDP_CONTROL
- MSR_FEATURE_CONFIG
- MSR_TURBO_ACTIVATION_RATIO
Also do the following as done on other SoCs:
- Configure VMX and lock it
- Enable LAPIC TPRs (fixes MWAIT support)
- Honor CONFIG_SET_MSR_AESNI_LOCK_BIT
- Set TCC thermal target as set in devicetree
Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT.
TEST: Booted on ocp/tiogapass to Linux 6.9 with all cores in
ACPI C6, no boot delay or hung tasks could be found.
Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85289
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented
in non-Lite CSE SKUs. Original CL [1] adding this feature also says
that, but at that point the feature was validated for CSE Lite only.
Move cse_get_boot_performance_data() to shared blk/cse/telemetry.c to
have it compile for mainboards without CSE Lite.
TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with
SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`:
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 34,000
945:CSE started to handle ICC configuration 172,000 (138,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000)
991:Die Management Unit (DMU) load completed 360,000 (46,000)
0:1st timestamp 385,844 (25,844)
11:start of bootblock 398,796 (12,952)
12:end of bootblock 402,099 (3,302)
[...]
[1]: https://review.coreboot.org/c/coreboot/+/59507
Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This change fixes building NovaCustom V540TU, which previously errored
out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition.
Replace soc/gpio_defs.h with gpio.h which includes everything we need,
same as it was done for ADL in change 71266, and other SoCs.
TEST=Build and boot NovaCustom V540TU
Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit enhances the SMBIOS Type 4 table by populating the "serial
number" field with the unique SoC QDF information retrieved via PMC
IPC.
This improvement provides more accurate and detailed processor
information for Panther Lake SoCs and onwards, aiding in:
- System identification
- Diagnostics
- Asset management
Previously, the serial number field was not populated.
TEST=Able to build and boot google/fatcat.
Example of SMBIOS Type 4 output:
Before this commit:
Serial Number: Not Specified
Asset Tag: Not Specified
Part Number: Not Specified
After this commit:
Serial Number: ABCD (Example SoC QDF information)
Asset Tag: Not Specified
Part Number: Not Specified
Change-Id: I38a0bb0e44c619393b8f058ae30fbf2f9719b724
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit introduces a new function,
`retrieve_soc_qdf_info_via_pmc_ipc()`, to retrieve the SoC QDF
information string using the PMC IPC mechanism.
This function allows for more flexible use of the SoC QDF information,
enabling its use in various data structures like the SMBIOS Type 4
table.
The existing `pmc_dump_soc_qdf_info()` function is updated to use this
new function to retrieve the QDF information before printing it.
TEST=Able to build and boot google/fatcat.
Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common
code fill in the SMBIOS type 17 entries for all slots and found DIMMs.
This also allows to build dimm.c unconditionally on all xeon_sp socs.
Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS.
Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix debug prints that use non-thread safe dev_path(). Since the code
is part of MPinit, it's using multiple threads and one threads modifies
the only buffer used, resulting in path being printed that do not belong
to the current thread.
Drop the call since printing the APIC ID is sufficient and thread safe.
Change-Id: I0cbc9cb11da8397ab6c2e8e56414558a8a0db93b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85288
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On 1st and 2nd gen Xeon-SP the VTD PCI device has different PCI IDs,
depending if it's on the CSTACK or PSTACK.
Make sure to handle all VTD device on all stacks the same.
For later SoCs this was already the case since the PCI devices have
the same PCI ID.
Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Generally the base address of FSP output is already aligned so there is
no need to minus 1. The current code loses 1 byte in the lower DRAM
address space.
Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85434
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
These header files do not seem to be used in coreboot. Presumably
they're left over after the code that used them was removed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ide70239c7c2e93fff548d989735450396308c62b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85370
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Change IPU name to 4 characters: IPU0
While the ACPI device name is 'IPU', some part of generated SSDT looks
for 'IPU_', since by convention, the names less than 4 characters is
padded with underscope ("_"). Please see APCI spec 5.3 ACPI Namespace.
BUG=none
TEST=Boot fatcat board to OS and check that IPU device name is IPU0 in
the SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I60ce2998cb1d97589c0f7544ce8dc92c12a2b8c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85274
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a Kconfig option to enable the UFS controller for
mainboards using the Intel Panther Lake-UH SoC.
By default, the UFS controller is disabled as it is not supported by
other SoC configurations. This prevents accidental enabling of the
UFS controller on unsupported platforms.
BUG=b:379828045
TEST=Built google/fatcat with and without UFS enabled.
Change-Id: Ica89ae85582367809128fc6cf0cd5fe5d40a2235
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85191
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change introduces Kconfig guards around the UFS workaround code
in the common ACPI ASL file. This ensures that these workarounds are
only applied when necessary, allowing future SoCs with UFS controllers
to reuse the common ASL file without modification.
By using Kconfig, we can enable or disable the workarounds based on
the specific SoC configuration, providing greater flexibility and
maintainability.
BUG=b:379828045
TEST=Able to compile google/fatcat.
Change-Id: I968b8811e508378a36648bd8234ff0fd7237b00d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85208
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Drop duplicated fields
- Drop fields filled with constant values
- Drop SRAT prefix for sysmemmap entries
- Print all zeros when concatenating two hex numbers
Change-Id: I379aeb6fcd2e28665c7d592b0639db3c1b4caa9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85189
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates Kconfig that selects ME specification version for
Pantherlake SoC from version 18 to version 21.
BUG=b:362647201
TEST=Able to build fatcat with SOC_INTEL_COMMON_ME_SPEC_21 selected.
Change-Id: Ibfebd7c093240aa7f1d6337f3e4dd6e5d34bed1d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85187
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch introduces Kconfig support for Intel's Management Engine
(ME), version 21. When 'SOC_INTEL_COMMON_BLOCK_ME_SPEC_21' is selected
it sets the ME_SPEC configuration to 18 because ME version 21 is
compatible with version 18 in terms of Host Firmware status registers.
BUG=b:362647201
TEST=Able to build fatcat after selecting SOC_INTEL_COMMON_ME_SPEC_21
Change-Id: I90c946751ac530dac1af4ff9c3c921b5faf82448
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch enables coreboot to perform CPU feature programming for both
the Boot Strap Processor (BSP) and Application Processors (APs) on
Intel Panther Lake platforms.
This change eliminates the need for the following FSP modules:
- CpuMpPpi
- CpuFeature
By handling CPU feature programming within coreboot, we reduce reliance
on external FSP binaries and improve code maintainability.
BUG=b:376092389, b/364822529
TEST=Built and booted google/fatcat successfully. Verified CPU features
are correctly programmed.
Change-Id: I73321485327f6a02ec8338fcfa1faf1e71008ba6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Walk the devicetree to collect all PCI IOAPICs. When found read
the IOAPIC base address from hardware.
TEST: On ocp/tiogapass all IOAPICs are found and advertised.
Change-Id: I2835c202e56849655795b96bc83862cb18e83fc0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84851
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPX uses the same PCU IDs as SKX.
Change-Id: I1bc96232e120b9cd9cb4f5b7b5df7d7db62fcbc4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84852
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On 1st and 2nd gen Xeon-SP the VTD PCI device is not at DEVFN 0.0.
Fix the DEVFN address and thus fix an assertion in vtd_probe_bar_size().
Change-Id: Ie879e95436af92fca1fee49135938ca2b005d579
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Drop DMAR_X2APIC_OPT_OUT since coreboot is able to enable X2APIC.
TEST: Works fine on OCP/tiogapass, thus drop the opt out.
Change-Id: Ia0443a39a9bf392976cfd1a7ccf6a335d5f0bd70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Set _PXM in ACPI to indicate which socket the PCI domain belongs to.
TEST: Booted on 2S ocp/tiogapass and checked dmesg that PCI domains are
advertised in the correct Proximity Domain.
Change-Id: I39cec0307b0dce0a4da5df5be5095b8d90758997
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Currently coreboot hardcodes the same IOAPIC IDs as used on UEFI native,
however FSP does not program the IOAPIC IDs, except for PCH IOAPIC.
Drop existing code that hardcodes PCI addresses and IOAPIC IDs and
detect the IOAPIC inside the domain automatically, read the IOAPIC
base address and let existing code figure out the IOAPIC ID by reading
it back from HW.
Change-Id: I2543a46dcc4a98ec8629530ca87882a7106c9ed1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84850
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Drop soc_get_stack_for_port() and move a comment.
Change-Id: I9d7615b633b344783150b3e1f3d98634630ed354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84844
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
General Purpose Memory Range registers are only used if extended BIOS
region is enabled now, this patch wraps the related code with Kconfig
item `CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW`.
Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one
of PIRQA-H. This patch adds a function itss_get_dev_pirq() returning
PIRQ for a given device and INT pin.
Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Remove <assert.h> when it is not used.
Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit adds an assertion to ensure that the values of
pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the
soc_intel_<soc>_config structure are unique.
This check helps to catch potential configuration errors early on,
preventing unexpected behavior during system initialization.
TEST=Built and booted normally. No assertion failure observed.
Able to catch the hidden issue due to overlapping Tier 1 GPE
configuration.
[DEBUG] CPU: Intel(R) Core(TM) 3 N355
[DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a
[DEBUG] CPU: AES supported, TXT supported, VT supported
...
...
[DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N
[DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU
[DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1
[EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c',
line 163
Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
