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soc/intel/xeon_sp/cpx: Add missing FADT fields

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CPX uses the same PCH as SKX does, thus it has the same ACPI timer
timer and PM2 control fields as SKX.

Copy the code from skx to cpx to reduce code differences. Allows to
merge both codebases into one.

Change-Id: I92fc63a6655fb915b2c06273c3259dddfb93e8bb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2024-12-03 09:49:24 +01:00 • committed by Lean Sheng Tan
commit 94d200c394
1 changed files with 16 additions and 2 deletions
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18
src/soc/intel/xeon_sp/cpx/soc_acpi.c
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@ -36,8 +36,22 @@ uint32_t soc_read_sci_irq_select(void)
void soc_fill_fadt(acpi_fadt_t *fadt)
{
/* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */
fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE);
const uint16_t pmbase = ACPI_BASE_ADDRESS;
/* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */
fadt->flags &= ~(ACPI_FADT_SEALED_CASE);
fadt->flags |= ACPI_FADT_SLEEP_TYPE;
fadt->pm2_cnt_blk = pmbase + PM2_CNT;
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
/* PM Extended Registers */
fill_fadt_extended_pm_io(fadt);
}
void soc_power_states_generation(int core_id, int cores_per_package)