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soc/intel/alderlake: Add support for PCIe speed setting

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This change provides config for devicetree to control PCIe speed

BUG=b:374205496
TEST=build pass

Change-Id: I32a9918a51faa903927a9646605a618744b527c0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
David Wu 2024-12-06 15:36:05 +08:00 • committed by Subrata Banik
commit d5a11293ff
2 changed files with 29 additions and 0 deletions
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17
src/soc/intel/alderlake/fsp_params.c
View file

@ -490,6 +490,12 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
* | | PchPcieL1SubstatesL1_1 | | |
* | | PchPcieL1SubstatesL1_1_2 | | [Default] |
* | | PchPcieL1SubstatesMax | [Default] | |
* |-------------------|--------------------------|-----------|-----------|
* | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto | [Default] | |
* | | PchPcieRpPcieSpeedGen1 | | |
* | | PchPcieRpPcieSpeedGen2 | | |
* | | PchPcieRpPcieSpeedGen3 | | |
* | | PchPcieRpPcieSpeedGen4 | | |
* +-------------------+--------------------------+-----------+-----------+
*/
@ -527,6 +533,15 @@ static unsigned int adl_l1ss_control_to_upd(enum L1_substates_control l1_substat
return UPD_INDEX(l1_substates_control);
}
static unsigned int adl_pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control)
{
/* Use auto unless overwritten */
if (!pcie_speed_control)
return UPD_INDEX(SPEED_AUTO);
return UPD_INDEX(pcie_speed_control);
}
static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
const struct pcie_rp_config *rp_cfg,
unsigned int index)
@ -537,6 +552,8 @@ static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
s_cfg->PcieRpL1Substates[index] =
adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
s_cfg->PcieRpPcieSpeed[index] =
adl_pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed));
}
/*

12
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View file

@ -58,6 +58,16 @@ enum ASPM_control {
ASPM_AUTO,
};
/* This enum is for passing into an FSP UPD, typically PCIe Speed */
enum PCIE_SPEED_control {
SPEED_DEFAULT,
SPEED_AUTO,
SPEED_GEN1,
SPEED_GEN2,
SPEED_GEN3,
SPEED_GEN4,
};
/* PCIe Root Ports */
struct pcie_rp_config {
/* CLKOUT_PCIE_P/N# used by this root port as per schematics. */
@ -71,6 +81,8 @@ struct pcie_rp_config {
enum ASPM_control pcie_rp_aspm;
/* timeout for device detect */
uint32_t pcie_rp_detect_timeout_ms;
/* PCIe RP PCIe Speed */
enum PCIE_SPEED_control pcie_rp_pcie_speed;
};
/*