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soc/intel/xeon_sp: Walk devicetree to find IOAPICs

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Walk the devicetree to collect all PCI IOAPICs. When found read
the IOAPIC base address from hardware.

TEST: On ocp/tiogapass all IOAPICs are found and advertised.

Change-Id: I2835c202e56849655795b96bc83862cb18e83fc0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84851
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2024-10-24 14:04:46 +02:00 • committed by Lean Sheng Tan
commit 3a891aff8c
1 changed files with 22 additions and 20 deletions
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42
src/soc/intel/xeon_sp/iio_ioapic.c
View file

@ -1,38 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <arch/ioapic.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <intelblocks/acpi.h>
#include <soc/chip_common.h>
#include <soc/util.h>
#include <soc/pci_devs.h>
#include <stdint.h>
static uintptr_t xeonsp_ioapic_bases[CONFIG_MAX_SOCKET * MAX_IIO_STACK + 1];
size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
{
struct device *dev = NULL;
int index = 0;
const IIO_UDS *hob = get_iio_uds();
*ioapic_bases = xeonsp_ioapic_bases;
for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) {
if (!soc_cpu_is_enabled(socket))
/*
* Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
* The IIO IOAPIC is placed at 0x1000 from the reported base.
*/
xeonsp_ioapic_bases[index++] = IO_APIC_ADDR;
while ((dev = dev_find_class(PCI_CLASS_SYSTEM_PIC << 8, dev))) {
if (!is_pci_ioapic(dev))
continue;
for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
const STACK_RES *ri =
&hob->PlatformData.IIO_resource[socket].StackRes[stack];
uint32_t ioapic_base = ri->IoApicBase;
if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF)
continue;
xeonsp_ioapic_bases[index++] = ioapic_base;
/*
* Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
* The IIO IOAPIC is placed at 0x1000 from the reported base.
*/
if (socket == 0 && stack == 0) {
ioapic_base += 0x1000;
xeonsp_ioapic_bases[index++] = ioapic_base;
}
}
u16 abar = pci_read_config16(dev, APIC_ABAR);
if (!abar)
continue;
const u32 addr = IO_APIC_ADDR | ((abar & 0xfff) << 8);
printk(BIOS_DEBUG, "%s: %s: IOAPIC Address: 0x%x\n",
__func__, dev_path(dev), addr);
xeonsp_ioapic_bases[index++] = addr;
}
return index;