soc/intel/pantherlake: Add option to enable UFS controller

This patch adds a Kconfig option to enable the UFS controller for
mainboards using the Intel Panther Lake-UH SoC.

By default, the UFS controller is disabled as it is not supported by
other SoC configurations. This prevents accidental enabling of the
UFS controller on unsupported platforms.

BUG=b:379828045
TEST=Built google/fatcat with and without UFS enabled.

Change-Id: Ica89ae85582367809128fc6cf0cd5fe5d40a2235
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85191
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/pantherlake/Kconfig

@@ -421,4 +421,8 @@ config SOC_PHYSICAL_ADDRESS_WIDTH
 	int
 	default 42
 
+config SOC_INTEL_UFS_CLK_FREQ_HZ
+	int
+	default 38400000
+
 endif

src/soc/intel/pantherlake/acpi/southbridge.asl

@@ -49,6 +49,8 @@
 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
 
 /* UFS 0:17:0 */
-/* TODO: Add ufs.asl entry for PTL-U SKU */
+#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+#include <soc/intel/common/block/acpi/acpi/ufs.asl>
+#endif
 
 #endif

src/soc/intel/pantherlake/chipset.cb

@@ -143,6 +143,7 @@ chip soc/intel/pantherlake
 		device pci 16.1 alias heci2 off end
 		device pci 16.4 alias heci3 off end
 		device pci 16.5 alias heci4 off end
+		device pci 17.0 alias ufs off end
 		device pci 18.0 alias eheci1 off end
 		device pci 18.1 alias eheci2 off end
 		device pci 18.2 alias eheci3 off end

src/soc/intel/pantherlake/fsp_params.c

@@ -658,6 +658,20 @@ static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->IaxEnable = is_devfn_enabled(PCI_DEVFN_IAA);
 }
 
+static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg,
+		const struct soc_intel_pantherlake_config *config)
+{
+#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+	/* Setting FSP UPD (1,0) to enable controller 0 */
+	s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS);
+	s_cfg->UfsEnable[1] = 0;
+#else
+	/* Setting FSP UPD (0,0) to keep both controllers disabled */
+	s_cfg->UfsEnable[0] = 0;
+	s_cfg->UfsEnable[1] = 0;
+#endif
+}
+
 static void arch_silicon_init_params(FSPS_ARCH2_UPD *s_arch_cfg)
 {
 	/* Assign FspEventHandler arch Upd to use coreboot debug event handler */
@@ -696,6 +710,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		fill_fsps_npu_params,
 		fill_fsps_audio_params,
 		fill_fsps_iax_params,
+		fill_fsps_ufs_params,
 	};
 
 	for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)

src/soc/intel/pantherlake/include/soc/pci_devs.h

@@ -139,6 +139,12 @@
 #define  PCI_DEV_CSE_3		_PCI_DEV(CSE, 4)
 #define  PCI_DEV_CSE_4		_PCI_DEV(CSE, 5)
 
+#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+#define PCI_DEV_SLOT_UFS	0x17
+#define  PCI_DEVFN_UFS		_PCI_DEVFN(UFS, 0)
+#define  PCI_DEV_UFS		_PCI_DEV(UFS, 0)
+#endif
+
 #define PCI_DEV_SLOT_ESE	0x18
 #define  PCI_DEVFN_ESE1		_PCI_DEVFN(ESE, 0)
 #define  PCI_DEVFN_ESE2		_PCI_DEVFN(ESE, 1)

src/soc/intel/pantherlake/include/soc/ufs.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Panther Lake Processor PCH Datasheet
+ * Document number: TBD
+ */
+
+#ifndef _SOC_PANTHERLAKE_UFS_H_
+#define _SOC_PANTHERLAKE_UFS_H_
+
+#include <soc/pci_devs.h>
+
+/* Calculate _ADR for Intel UFS Controller */
+#define UFS_ACPI_DEVICE (PCI_DEV_SLOT_UFS << 16 | 0x0007)
+
+#define R_SCS_CFG_PCS		0x84
+#define R_SCS_CFG_PG_CONFIG	0xA2
+
+#endif