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soc/intel/pantherlake/acpi: Update camera_clock_ctl.asl

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Fix ISCLK register definitions

Reference: 813032 - Panther Lake H I/O Registers

BUG=b:357011633
TEST=check camera functionality on fatcat

Change-Id: Ie9f1f639970344eb359dee37914ee26a02dcfb4b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85058
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Bora Guvendik 2024-11-08 14:23:41 -08:00 • committed by Subrata Banik
commit 73d1980d23
1 changed files with 7 additions and 3 deletions
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src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
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@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#define R_ICLK_PCR_CAMERA1 0x8000
#define B_ICLK_PCR_FREQUENCY 0x1
#define B_ICLK_PCR_REQUEST 0x2
#define B_ICLK_PCR_FREQUENCY 0x3
#define B_ICLK_PCR_REQUEST 0x4
/* The clock control registers for each IMGCLK are offset by 0xC */
#define B_ICLK_PCR_OFFSET 0xC
@ -32,7 +32,11 @@ Scope (\_SB.PCI0) {
/*
* Clock control Method
* Arg0: Clock source select (0 .. 5 => IMGCLKOUT_0 .. IMGCLKOUT_5)
* Arg1: Frequency select (0: 24MHz, 1: 19.2MHz)
* Arg1: Frequency select
* 2'b00 - 19p2 XTAL
* 2'b01 - 19p2 IMG
* 2'b10 - 19p2 RTC
* 2'b11 - 24 IMG
*/
Method (MCON, 0x2, NotSerialized)
{