soc/intel/xeon_sp/cpx: Fix register lock

Do not use a define for a PCI register to lock a MSR.

The defines will be moved in the following commit to it's own header,
preventing the use in CPX CPU init.

Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/xeon_sp/cpx/cpu.c

@@ -115,10 +115,8 @@ static void each_cpu_init(struct device *cpu)
 	set_vmx_and_lock();
 	set_aesni_lock();
 
-	/* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
-	   Lock Turbo. Did FSP-S set this up??? */
 	msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
-	msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK);
+	msr.lo |= BIT31;	/* Lock it */
 	wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
 }