While helping with board bringup, I noticed that CRB is enabled in mFIT
but it was missing in board code.
Change-Id: I8f34cac2508ef15f5b6f6542a912fb12af3c2dbf
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: KunYi Chen <kunyi.chen@gmail.com>
dev->path.gicc_v3.mpidr is an unsigned long long, so the format
specifier should be %llx, not %x. Keep the minimum 2 digit output.
BUG=CID 1611971
Change-Id: I126b0281efcba2c3e41cf6da4d006b8d2eb7215b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Generate RAM ID for
IC SDRAM(315P) MT62F1G32D2DS-023 WT:C
IC SDRAM(315P) H58G56CK8BX146
IC SDRAM(315P) K3KL8L80EM-MGCU(FBGA)
DRAM Part Name ID to assign
MT62F1G32D2DS-023 WT:C 7 (0111)
H58G56CK8BX146 7 (0111)
K3KL8L80EM-MGCU 7 (0111)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I7ff2f2d43784a6034c1262913dbeaffc1dc3036f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Counting the entries on the verb table, there are 10 "AZALIA_" macros
and 44 32-bit values. Therefore, the correct amount of entries should be
10 + (44 / 4) = 21.
Change-Id: Ic858d9076d12755014caa28e428d57dde0ef375d
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the DRAM_ID 0 memory part from the H58G56BK7BX068 memory part
to H58G56BK8BX068 for ocelot.
BUG=b:437989448
TEST=`emerge-ocelot coreboot chromeos-bootimage', flash and boot
ocelot and verify it's able to train memory without error.
Change-Id: I979a75f770cc5bf82b7c5537e4c36651ecc21ea6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88759
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our strsep() function is slightly incorrect in that it leaves the
`stringp` pointer pointing to the terminating NUL byte after parsing the
last token. The man page for official implementations says:
> In case no delimiter was found, the token is taken to be the entire
> string *stringp, and *stringp is made NULL.
This doesn't affect things in practice much because we also
(incorrectly) return NULL when called with `**stringp == '\0'`, meaning
the usual pattern of calling `strsep()` in a row without checking
results first still works when there are less tokens than expected,
since we terminate early from that case instead. But it does break the
edge cases where the caller wants to check if there were extra bytes
beyond the last token (`stringp == NULL`), and where we call `strsep()`
on a pointer pointing directly to a terminating NUL byte already
(supposed to return an empty string but our implementation actually
returns NULL). It doesn't look like these edge cases occur anywhere in
current libpayload or depthcharge code.
This patch fixes the issue and also adds a unit test to ensure it
remains correct in the future. (Also move the definition of the `errno`
variable from lib.c into string.c, because `perror()` in string.c is the
only function that actually needs that, and the crazy linker error you
get when only linking one but not the other into a test will waste you
half an hour to figure out.)
Change-Id: I610b5117710c110bcba4fac2a0bb6c13f4f8d046
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88729
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rearm and clear functions are called only if a valid crashlog is
present and extracted. If there is no valid crashlog, rearming will
lead to incorrect notification and skipping of the next crashlog event
BUG=b: None
TEST= PMC discovery buffer - rearmed status bit (trig_armed_sts)
MMIO read of Bit position 25 is rearmed status bit
MMIO read of desc_table_addr = (bar_address + offset)
desc_table_addr = 0x9c198000 + 0x1d00 = 0x9c199d00
:1 for cold boot and
:0 for warm boot after manual crash
Change-Id: I42da487abd383567d7945835b738557e2e3fa714
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
After crashlog data is extracted, CPU rearm command is issued to
prepare the crash logging mechanism for future events. Instead of
command and response polling of mailbox, watcher interface which is a
direct MMIO based, low latency control register is used for efficiency.
In PTL, a Crashlog watcher providing control the same way provided by
Crashlog Mailbox Interface used by (mainly) BIOS is used for all CPU
crashlog control requests from BIOS to PUNIT.
BUG=b: None
TEST= Manually trigger crash using command
iotools mmio_write32 (baraddress + watcher offset=0x10) 0x20000000
followed by warm boot, check rearm status - which is 25th bit of
*(bar_address)
Change-Id: I89dd23fad144c1c7122b5536f1ac848ea66ea6b1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set I2C2, I2C3, and I2C4 controllers to disabled in serial_io_i2c_mode
Remove configuration for I2C2, I2C3, and I2C4 from common_soc_config
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: Ibe26bde3ffbd4b188584369cdd686ffb116d6a7d
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88650
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
According to MediaTek, this delay was added in the driver bring-up stage
to mitigate the display garbage issue. Now, the delay can be removed.
BUG=b:434574691
TEST=Check FW screen on Navi
Change-Id: I5408d95be7a4aaf8bb4bb639c319320514c4fd99
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Meaure the execution time for following eDP functions.
- dptx_check_sinkcap
- dptx_get_edid
- dptx_set_trainingstart
- mtk_edp_init
These dptx_* functions are the primary contributors to the execution
time of mtk_edp_init, which is only called in dev/recovery mode. This
insight can be used for future boot time optimization by breaking down
the eDP initialization process.
TEST=Boot with DEV mode using the boot image without serial console
support.
TEST=cbmem -c|grep "done after"
[INFO ] dptx_check_sinkcap done after 38 msecs
[INFO ] dptx_get_edid done after 294 msecs
[INFO ] dptx_set_trainingstart done after 100 msecs
[INFO ] mtk_edp_init done after 438 msecs
Change-Id: I7aabf3a33b9628f20fe16980033b00de9afc44e6
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
mtk_edp_init is similar in dptx_v1.c and dptx_v2.c. Make mtk_edp_init
common by
1. Extract dptx_set_tx_power_con and dptx_set_26mhz_clock to
edp_power_on.
2. Add dptx_hal_phy_init weak function for the platform which does not
require initialization.
TEST=emerge-cherry coreboot && emerge-rauru coreboot
Change-Id: I686208c6bf8538354fb4fd238755899b0ef8f86b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The commit adds new memory regions for the CPUCP (CPU Subsystem Control
Processor) and TZ (TrustZone) components to the x1p42100 SoC. This is
necessary to properly reserve the memory used by these firmware
components during boot.
The changes involve:
- Declaring new memory regions dram_cpucp_dtbs, dram_cpucp, dram_tz,
and dram_tz_rem in the symbols_common.h header.
- Defining the base addresses and sizes for these new regions in
memlayout.ld.
Registering these memory ranges as reserved in the soc_read_resources
function in soc.c so that coreboot does not overwrite them.
TEST=Able to load aop firmware while booting google/quenbi without
boot hang.
Change-Id: I1ecbc1e5ea420b7bdd5518612082ca0e14b35f6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Suggested-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Caboc schematic 0702 uses a MOS reverse pin to connect
GPP_A21(WWAN_FWUPD) to WWAN(PERST). The WWAN_PERST is a low active pin.
Change GPP_A21 and overridtree setting based on the above description.
BUG=b:437017620
TEST=emerge-brox coreboot
WWAN module is enumerated in lspci
modem status can find WWAN module
Change-Id: I3b75b53f0e5731b2fec48634c672a6432acdde7f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Commit 32b944b77a ("mb/google/brox/var/caboc: Update hda_verb table"), CB:88627 didn’t update the number of jacks, so do it now.
BUG=b:435345756
TEST=emerge-brox coreboot
check system audio output is fine
Change-Id: Id559ceba2d5c21b120c76147bf042520e57865a7
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88644
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This patch adds support to skip DDR training when valid training data
is available in flash.
The exact size of the training data is passed to ensure accurate hash
computation. A hash is computed on the DDR training data using the
specified size and compared with the stored hash in the header. This
requires passing only the exact training data size to ensure correct
validation.
TEST=Create an image.serial.bin and ensure it boots on X1P42100. Verify
that the DDR training is skipped when valid data is available in flash.
w/o this patch: doing RW_MRC_CACHE update in every boot.
```
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG] read SPI 0xc1f290 0xf27c: 5010 us, 12390 KB/s, 99.120 Mbps
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
```
w/ this patch: no need to perform RW_MRC_CACHE update.
```
[DEBUG] FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG] read SPI 0xc10024 0xf268: 5016 us, 12371 KB/s, 98.968 Mbps
```
Change-Id: I1a5ad0766ea77b22e6a8cb97c24a90c24629dfd0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88742
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Because the EQ tuning is different from type-c C1 port in
pujjolo and pujjoquince daughter board, so use fw config to
assign the specific PDC fw.
BUG=b:436445362
TEST= Build and boot to OS and check PDC FW version.
Change-Id: Id9ce85e40e919ab572ce1c560b4daf3c977de682
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88698
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because of preventing S0ix fail caused by wlan, so according to
intel suggestion, add wlan rtd3 setting.
BUG=b:422600523
TEST= Build and boot to OS and check S0ix test using
`suspend_stress_test -c 5` work fine.
Change-Id: I959da35d60e0da058727519d6db082ea415dbe2a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Updated the memory layout file to include necessary DDR region
reservations for AOP and BL31.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I67b0210dfc563c0a0e8f879b1f41693e1d0e6384
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Introduce a new `SOC_QUALCOMM_HAMOA` Kconfig option and refactor the
Qualcomm SoC build to support Hamoa.
This change prepares the groundwork for Hamoa-based mainboards by:
- Creating a common base: A new `SOC_QUALCOMM_BASE` Kconfig option
is introduced to group configurations shared between Qualcomm SoCs.
- Separating SoC-specific blobs: The build process now dynamically
selects the correct device tree blob (DTB) and display control blob
(DCB) files for Hamoa via a new `DTB_DCB_BLOB_PATH` variable in the
`Makefile.mk`.
- Enabling future mainboards: This allows mainboards built on the Hamoa
SoC to be configured and built within the existing Qualcomm SoC
directory.
BUG=b:437662790
TEST=Able to build and boot google/quenbi.
Change-Id: Ife983495b757fbf06ad96f0ca15fd89bf41c77c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88737
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the Pmic.bin file from the coreboot filesystem
(CBFS) and the Makefile.mk for the Qualcomm x1p42100 SoC.
The PMIC file is no longer used in the boot process. It's safe to
remove it to reduce the size of the final coreboot image and clean
up the build configuration.
TEST=Able to build and boot google/quenbi.
Change-Id: Iac8e4b32677f36959323a5dd3a5c7f88a6359720
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88736
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change addresses GCC-15 behavior where {0} union initializers only
clear the first member, leaving padding bits uninitialized. The new {}
initializer ensures full union clearing as required by C23.
Change-Id: I1d9b063d8bdd3d2f0b0f67e6c20eb484ff6a5cc5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add WIFI SAR table for intel WIFI SAR table
BUG=b:434861866
TEST=Build and flash to DUT, check that SAR table is loaded by cbmem -c | grep SAR
Change-Id: Idf48254ec43535ff51859ecbec3ea75b7c35e70c
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The HP ProDesk 600 G1 SFF comes with a mainboard named "Merlin Rev.A"
which is also used by the EliteDesk 800 G1 SFF and Z230 SFF series.
Differences are in available USB2, USB3 and SATA (headers / ports)
, PCIe (slots / length), video outputs (number / type) or chipset used.
While the EliteDesk 800 G1 SFF shares the same OEM BIOS update file, the
Z230 SFF differs. This port was made on a model with 2 DP / DP++, 1 VGA,
4 USB2 and 2 USB3 backpanel ports, 4 SATA ports and 4 PCIe slots
(1 16x and 3 1x length) using a Q85 chipset (without heat sink).
Model: HP ProDesk 600 G1 SFF Business PC
Regulatory Model: TPC-F046-SF
Product No. J0E94ET#ABH, PROMO600PDeSi54590500hq4X46k NL (C8T44AV)
Mainboard: Merlin Rev.A, 795972-001
Pure autoport (initial commit) doesn't boot, more patches will bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, devicetree edits enabled all PCIe ports and some NPCD379
code from other HP desktops makes most superio related functions work.
Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L12873F in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!
Tested:
- coreboot 25.06-77-g812d0e2f626d as base
- EDK2 (MrChromebox/2502)
- SeaBIOS 1.16.3
- Broadwell mrc.bin (tidus)
- Haswell mrc.bin (peppy)
- Haswell NRI
- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
- both DP / DP++ (HDMI) & VGA output available during POST, BOOT and OS
- Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
- RAM 1/2/3/4 slots filled using mixed 1.35 / 1.5v 1333 / 1600MHz DIMMs
(NRI & mrc.bin)
0/1: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
1/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
0/3: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
- Fedora MATE 42 (Kernel 6.14)
- KDE NEON 6.4 (Kernel 6.11)
- MS Windows 10 / 11
- Audio Outputs: 2x DP, Headphone, Line Out, Speaker (left&right chan.)
- Audio Input: Line In (back)
- USB2/3 all ports (including internal headers)
- Intel I217-LM Gb LAN
- SATA 4 ports
- PCIe 16x slot @2.5GT/s (or 8x @8GT/s) and three 1x slots @5GT/s
- dGPU nVidia GeForce GT640-2GD3 / AMD Radeon RX460 4GB (PCIe 8x)
(disabled Hide PEG devices, option ROMs load in SeaBIOS & EDK2)
- PS/2 ports (both Keyboard and Mouse)
- Serial port (coreboot console & OS)
- PowerButton (Poweron/Poweroff/Wake)
- LEDs HDD & POWER (both off during suspend)
- Shutdown/Reboot/Suspend
- power_on_after_fail= Disable / Enable / Keep
- Strip down the Intel ME/TXE firmware (make menuconfig)
- Disabling ME HECI (manually disable in devicetree.cb)
- flashrom -p internal -c "MX25L12835F/MX25L12873F" #(read & write)
Not tested:
- COMB (serial port header)
- PAR (parallel port header)
- Audio Input Microphone Port (front)
- USBDEBUG PORT
- VBIOS
Not working:
- CMOS checksum errors only on psu_fan_lvl resets to defaults sometimes
- dual GPU (iGPU shows visual glitches while dGPU works fine)
This occurs on both Broadwell, Haswell mrc.bin and Haswell NRI,
may show i915 error in dmesg after waking from suspend!
All dGPU testing have been done with a cheap PCIe riser cable!
- Disable Intel ME PCI interface (make menuconfig)
- PSU FAN control its either full OFF or full ON see instruction!
- TPM Windows 10/11 detects it but "bios failed to communicate error"
- Wake on LAN (Power on from coldboot work, but not wake from suspend)
PSU FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!
NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.
The data.vbt blob was extracted using debugfs from the OEM firmware
v2.65 enabling both Displayport / DP++ (HDMI) and VGA video outputs.
Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.
Change-Id: If1082e0b56364f32e43f954b589fa627cbaee50c
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88616
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because RF team verified the P-sensor related function and
give suggestion that follow pujjoga's setting.
BUG=b:411558536
TEST=Build and boot to OS and check with RF team.
Change-Id: I938505af02d9d3f5ba98f34fef58b67b48f049db
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88703
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Crashlog storage and power management in PTL is changed to a unified
and persistent model,removing the need for manual SRAM power-down
commands after crashlog extraction.
Change-Id: I5bea1c816bbb68a4b2b21cc3be6cf118b4282fe7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88512
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
SPC741D8-2L2T/BCM is a Xeon SP 4th/5th gen (Eagle Stream) platform with:
- 1 SPR socket, 8 DDR5 DIMMs each
- 4x PCIe 5.0 / CXL 1.1 x16 slots
- 2x MCIO PCIe 5.0 x8 and 1 MCIO on PCH
- 2x M.2 PCH PCIe slots
- 2x 10 Gbit/s NIC and 2x 1 Gbit/s i210 NIC
It has an AST2600 BMC for remote management and most SuperIO functions
such as serial and an additional Nuvoton NCT6796D-E for others.
Working:
- All CPU cores of a 4/5th-gen Xeon SP are available at full speed
- All 8 memory DIMMs (KSM48R40BS8KMM-16HMR) with 32 bit execution
- All 4 PCIe slots
- On-board USB ports
- Video output via the AST2600 (on-board VGA)
- M.2 devices
Untested:
- TPM header
Not working:
- Serial port I/O, related to the AST2600 SuperIO not being located at
the default address of 0x2E (it uses 0x4E instead).
- PC speaker (buzzer), for the same reason.
- M.2 SSDs only use PCIe 3.0 x2, however, they should be capable of
PCIe 3.0 x4 speeds, which can be observed using the vendor firmware.
- Using more than 1 DIMM with 64 bit execution (the FSP
temp_ram_exit function never returns)
TEST=build/boot to Linux 6.12 using mainline edk2
Change-Id: I5b00a6f4ee68f71203940644860bf095615a9412
Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Co-authored-by: Felix Zimmer <felix.zimmer@student.kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in b:420800911#comment1
BUG=b:420800911
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5fe20642505be50194084cd859e8fa20b4127dd0
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88554
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because there is a pop noise when bios booting stage, so modify
verb table to fix the issue.
Change description by vendor:
The Class-D K DC function has been added (which is the main solution
this time), along with enabling silence detect to filter out noise
below -84 dB to prevent it from being played through the speaker.
BUG=b:430749506
TEST= Build and boot to OS, and check by EE and Realtek vendor.
Change-Id: I3ac6cc82daf2ea78e73392ad67a5f4da131ddef5
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88623
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Increase the size of the Memory Reference Code (MRC) cache to prevent
boot failures.
Previously, the MRC cache was 64K (32K for recovery and 32K for
read/write), which was insufficient for the firmware. This change
expands the UNIFIED_MRC_CACHE to 128K, with RECOVERY_MRC_CACHE and
RW_MRC_CACHE each receiving 64K.
BUG=b:437402936
TEST=Able to build and boot google/quenbi till depthcharge.
w/o this patch:
```
[ERROR] REGF metadata allocation failed: 3880 data blocks 2048 total blocks
[ERROR] MRC: failed to update 'RW_MRC_CACHE'.
```
w/ this patch:
```
[DEBUG] FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
...
[DEBUG] FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG] read SPI 0xc10010 0xf27c: 5011 us, 12387 KB/s, 99.096 Mbps
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
[INFO ] REGF update can't fit. Will empty.
[DEBUG] SF: Successfully erased 65536 bytes @ 0xc10000
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
```
Change-Id: Ie456f9ab870eab06c2d23cb5d2734faf644a2176
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Commit 8dec5fcaf8 ("drivers/spi: Add 4-byte address mode flag to
lb_spi_flash") split the existing 32-bit `erase_cmd` field into multiple
fields. The new `flags` field thus created is used to pass information
about whether the flash is in 4-byte address mode.
Unfortunately, we forgot to initialize the new fields in the case that
the flash is not in 4-byte address mode. This means it can have any
arbitrary value, including values where the new flag bit is accidentally
set (causing flash access errors in the payload).
This patch fixes the problem and tries to prevent further issues with
field changes in the future by explicitly zeroing the entire coreboot
table structure before starting to fill in the values.
Change-Id: I3ad9812fc76ae2989dcf4a294034c4e31456c74e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The properties of PARA3406 and PARA3408 are the same
Update PARA3406&PARA3408 to PARA340X
BUG=b:417106542
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchscreen works.
Change-Id: Ifed5dd9c2b0512c700f5262d7105578bc604a945
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88705
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setup GPP_C0 and GPP_C1 in early and romstage to meet spec requirements
Spec require TP_Reset ON after VTSP ON 0-10ms.
Before modification，TP_Reset ON before VTSP ON.
After modification，TP_Reset ON after VTSP ON 1ms.
BUG=b:421455835
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence
Change-Id: I7d3d79c9f67edf42b64316757c448fe385207a86
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8.
The slope of the voltage measured by the oscilloscope 4 mV/us is close to the theoretical value of 3.75 mV/us.
BUG=b:404416910
TEST=emerge-brox coreboot chromeos-bootimage
USE=fw_debug confirm SlowSlewRate set to 2 at FSP
Change-Id: I7ec05c6a20997fcc094b20fa763eb3bc030fefa1
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88696
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update DTT settings according to b:436759545#comment1 in
order to increase the limit of the charging current to 3A/1.5A.
BUG=b:436759545
TEST=emerge-nissa coreboot, and thermal engineer verifies OK.
Change-Id: I3f07884b2817904925050ef24957b5070a8cab65
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88699
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Set disable_progress_bar to disable the memory progress bar for fatcat
board. Removed the memory progress bar feature to enhance performance.
BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar is
disable.
Change-Id: Ic303aa57843039f49130c09da0345f7e7573b0e5
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88613
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Set disable_progress_bar to disable the memory progress bar for fatcat
board. Removed the memory progress bar feature to enhance performance.
BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar is
disabled.
Change-Id: I25302f6ed095603150d8e7e0bbe04ff96944f07c
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Move ICH7 GPIO register defines into private scope. This enforces
the use of GPIO common code and mainboard can no longer directly
access GPIO I/O registers.
Change-Id: Iedf3e55f8aecf7b1ac6f47b29d9f88d58d1b6867
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of directly accessing GPIO I/O registers use existing
common code to read the SPD pin straps.
Change-Id: Ie758a4bfb35d1f81c16537cda0e26e43ac860b1e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce a new helper function to set the INVERT bits on
the first GPIO bank. Use it on google link instead of using
a custom implementation.
Change-Id: Icfdbc3dcae5678695b6fcc9dab7ff97d291963cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88565
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 87c9bb3994 ("soc/intel/adl: Fill in SPD data on both channels
of DDR5 memory") accidentally deleted the function
mem_init_override_channel_mask().
Additionally, skip checking for channel 0 while consuming the channel
disable mask.
BUG=none
TEST=CQ
Change-Id: I6217b2801e88b8ab98b2a3acaa0cb9580b05bb64
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88697
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add firmware name and update gpio pins GPP_B3 GPP_B4 for ISH
bug=b:434789824,b:434858349
TEST=Flash and boot to OS on kaladin, tested sensors work fine and unit can enter s0ix
Change-Id: Ia8dbf17a589a580116430cc4978b8d4ebbcf785e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88597
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit transitions the touchscreen power sequencing from static
coreboot GPIO configuration to ACPI-driven management using the
devicetree infrastructure for the Screebo variant.
BUG=b:430444353
TEST=Able to build and boot google/screebo. Verified touchscreen is
working as expected with this patch.
Change-Id: Ie3456032c232ac92ed7501c08b1c89b0ac274c8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88638
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
