- C 93.8%
- ASL 2.2%
- Makefile 1.1%
- C++ 0.5%
- Pawn 0.5%
- Other 1.8%
The HP ProDesk 600 G1 SFF comes with a mainboard named "Merlin Rev.A" which is also used by the EliteDesk 800 G1 SFF and Z230 SFF series. Differences are in available USB2, USB3 and SATA (headers / ports) , PCIe (slots / length), video outputs (number / type) or chipset used. While the EliteDesk 800 G1 SFF shares the same OEM BIOS update file, the Z230 SFF differs. This port was made on a model with 2 DP / DP++, 1 VGA, 4 USB2 and 2 USB3 backpanel ports, 4 SATA ports and 4 PCIe slots (1 16x and 3 1x length) using a Q85 chipset (without heat sink). Model: HP ProDesk 600 G1 SFF Business PC Regulatory Model: TPC-F046-SF Product No. J0E94ET#ABH, PROMO600PDeSi54590500hq4X46k NL (C8T44AV) Mainboard: Merlin Rev.A, 795972-001 Pure autoport (initial commit) doesn't boot, more patches will bring up general Haswell fixes, vendor/product naming corrected, RAM SPD MAP slot detection, devicetree edits enabled all PCIe ports and some NPCD379 code from other HP desktops makes most superio related functions work. Flash instructions: After setting the FDO jumper on the motherboard the whole ROM can be dumped, however writing is locked for some part of the BIOS region. An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona probe to flash the MX25L12873F in situ without any issues. Only the power of the USB programmer was used, and the board's main PSU was disconnected during flash! Tested: - coreboot 25.06-77-g812d0e2f626d as base - EDK2 (MrChromebox/2502) - SeaBIOS 1.16.3 - Broadwell mrc.bin (tidus) - Haswell mrc.bin (peppy) - Haswell NRI - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2) - both DP / DP++ (HDMI) & VGA output available during POST, BOOT and OS - Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3 - RAM 1/2/3/4 slots filled using mixed 1.35 / 1.5v 1333 / 1600MHz DIMMs (NRI & mrc.bin) 0/1: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30) 0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33) 1/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29) 0/3: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37) - Fedora MATE 42 (Kernel 6.14) - KDE NEON 6.4 (Kernel 6.11) - MS Windows 10 / 11 - Audio Outputs: 2x DP, Headphone, Line Out, Speaker (left&right chan.) - Audio Input: Line In (back) - USB2/3 all ports (including internal headers) - Intel I217-LM Gb LAN - SATA 4 ports - PCIe 16x slot @2.5GT/s (or 8x @8GT/s) and three 1x slots @5GT/s - dGPU nVidia GeForce GT640-2GD3 / AMD Radeon RX460 4GB (PCIe 8x) (disabled Hide PEG devices, option ROMs load in SeaBIOS & EDK2) - PS/2 ports (both Keyboard and Mouse) - Serial port (coreboot console & OS) - PowerButton (Poweron/Poweroff/Wake) - LEDs HDD & POWER (both off during suspend) - Shutdown/Reboot/Suspend - power_on_after_fail= Disable / Enable / Keep - Strip down the Intel ME/TXE firmware (make menuconfig) - Disabling ME HECI (manually disable in devicetree.cb) - flashrom -p internal -c "MX25L12835F/MX25L12873F" #(read & write) Not tested: - COMB (serial port header) - PAR (parallel port header) - Audio Input Microphone Port (front) - USBDEBUG PORT - VBIOS Not working: - CMOS checksum errors only on psu_fan_lvl resets to defaults sometimes - dual GPU (iGPU shows visual glitches while dGPU works fine) This occurs on both Broadwell, Haswell mrc.bin and Haswell NRI, may show i915 error in dmesg after waking from suspend! All dGPU testing have been done with a cheap PCIe riser cable! - Disable Intel ME PCI interface (make menuconfig) - PSU FAN control its either full OFF or full ON see instruction! - TPM Windows 10/11 detects it but "bios failed to communicate error" - Wake on LAN (Power on from coldboot work, but not wake from suspend) PSU FAN instructions: If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is set to off the FAN will stay ON and will rampup after post in roughly a minute to its maximum RPM and will stay that way (current default)! NRI note: EDK2 shows 0GB instead of the actual RAM amount installed. While using Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted RAM modules have also been tested using NRI in Memtest86+ v7.20 which still correctly displays and test the total amount of RAM. The data.vbt blob was extracted using debugfs from the OEM firmware v2.65 enabling both Displayport / DP++ (HDMI) and VGA video outputs. Theoretically like the "compaq_8200_elite_sff" it should be possible to flash internally using a 2 step flash procedure using a minimized ME a small SeaBIOS based coreboot and a temporary flash layout inside the writeable BIOS region. Change-Id: If1082e0b56364f32e43f954b589fa627cbaee50c Signed-off-by: Walter Sonius <walterav1984@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88616 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| 3rdparty | ||
| configs | ||
| Documentation | ||
| LICENSES | ||
| payloads | ||
| spd | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| .mailmap | ||
| AUTHORS | ||
| COPYING | ||
| gnat.adc | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.mk | ||
| README.md | ||
| toolchain.mk | ||
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).
With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.
Source code
All source code for coreboot is stored in git. It is downloaded with the command:
git clone https://review.coreboot.org/coreboot.git.
Code reviews are done in the project's Gerrit instance.
The code may be browsed via coreboot's Gitiles instance.
The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.
Supported Hardware
The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.
For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.
Releases
Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.
All releases are available on the coreboot download page.
Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.
Build Requirements and building coreboot
The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.
To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.
That same page goes through how to use QEMU to boot the build and see the output.
Website and Mailing List
Further details on the project, as well as links to documentation and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://doc.coreboot.org/community/forums.html
Copyrights and Licenses
Uncopyrightable files
There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.
"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."
https://guides.lib.umich.edu/copyrightbasics/copyrightability
Similar terms apply to other locations.
These uncopyrightable files include:
- Empty files or files with only a comment explaining their existence. These may be required to exist as part of the build process but are not needed for the particular project.
- Configuration files either in binary or text form. Examples would be files such as .vbt files describing graphics configuration, .apcb files containing configuration parameters for AMD firmware binaries, and spd files as binary .spd or text *spd*.hex representing memory chip configuration.
- Machine-generated files containing version numbers, dates, hash values or other "non-creative" content.
As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.
If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.
Copyrights
The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.
Licenses
Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.
Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.
Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.
The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.
The Software Freedom Conservancy
Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.