mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
SPC741D8-2L2T/BCM is a Xeon SP 4th/5th gen (Eagle Stream) platform with: - 1 SPR socket, 8 DDR5 DIMMs each - 4x PCIe 5.0 / CXL 1.1 x16 slots - 2x MCIO PCIe 5.0 x8 and 1 MCIO on PCH - 2x M.2 PCH PCIe slots - 2x 10 Gbit/s NIC and 2x 1 Gbit/s i210 NIC It has an AST2600 BMC for remote management and most SuperIO functions such as serial and an additional Nuvoton NCT6796D-E for others. Working: - All CPU cores of a 4/5th-gen Xeon SP are available at full speed - All 8 memory DIMMs (KSM48R40BS8KMM-16HMR) with 32 bit execution - All 4 PCIe slots - On-board USB ports - Video output via the AST2600 (on-board VGA) - M.2 devices Untested: - TPM header Not working: - Serial port I/O, related to the AST2600 SuperIO not being located at the default address of 0x2E (it uses 0x4E instead). - PC speaker (buzzer), for the same reason. - M.2 SSDs only use PCIe 3.0 x2, however, they should be capable of PCIe 3.0 x4 speeds, which can be observed using the vendor firmware. - Using more than 1 DIMM with 64 bit execution (the FSP temp_ram_exit function never returns) TEST=build/boot to Linux 6.12 using mainline edk2 Change-Id: I5b00a6f4ee68f71203940644860bf095615a9412 Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu> Co-authored-by: Felix Zimmer <felix.zimmer@student.kit.edu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Fabian Meyer
Matt DeVillier
parent
b486c84b23
commit
fe6fa36504
15 changed files with 722 additions and 0 deletions
16
configs/builder/config.asrock.spc741d8
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16
configs/builder/config.asrock.spc741d8
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@ -0,0 +1,16 @@
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# This config is intended for ASRock Rack SPC741D8-2L2T boards based on Intel
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# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
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#
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# Type this in coreboot root directory to get a working .config:
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# make defconfig KBUILD_DEFCONFIG=configs/builder/config.asrock.spc741d8
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CONFIG_VENDOR_ASROCK=y
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CONFIG_BOARD_ASROCK_SPC741D8=y
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CONFIG_HAVE_IFD_BIN=y
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CONFIG_PAYLOAD_EDK2=y
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CONFIG_HAVE_ME_BIN=y
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CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
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CONFIG_IFD_BIN_PATH="site-local/eaglestream/descriptor.bin"
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CONFIG_ME_BIN_PATH="site-local/eaglestream/me.bin"
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CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
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CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
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39
src/mainboard/asrock/spc741d8/Kconfig
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39
src/mainboard/asrock/spc741d8/Kconfig
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@ -0,0 +1,39 @@
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if BOARD_ASROCK_SPC741D8
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_65536
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select IPMI_KCS
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select IPMI_KCS_ROMSTAGE
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select IPMI_OCP
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select MEMORY_MAPPED_TPM
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select MAINBOARD_HAS_TPM2
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select PLATFORM_USES_FSP2_X86_32
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select SOC_INTEL_SAPPHIRERAPIDS_SP
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select SUPERIO_ASPEED_AST2400
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select DRIVERS_ASPEED_AST2050
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select SUPERIO_NUVOTON_NCT6791D
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select HAVE_ACPI_TABLES
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select OCP_EWL
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select HAVE_INTEL_FSP_REPO
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select HAVE_X86_64_SUPPORT
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select PAGE_TABLES_IN_CBFS
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config MAINBOARD_DIR
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default "asrock/spc741d8"
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config MAINBOARD_PART_NUMBER
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default "SPC741D8-2L2T/BCM"
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config FMDFILE
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string
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
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config FSP_FD_PATH
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default "3rdparty/fsp/EagleStreamFspBinPkg/Fsp.fd"
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config MAX_SOCKET
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int
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default 1
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endif
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2
src/mainboard/asrock/spc741d8/Kconfig.name
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2
src/mainboard/asrock/spc741d8/Kconfig.name
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@ -0,0 +1,2 @@
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config BOARD_ASROCK_SPC741D8
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bool "SPC741D8-2L2T/BCM"
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8
src/mainboard/asrock/spc741d8/Makefile.mk
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8
src/mainboard/asrock/spc741d8/Makefile.mk
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@ -0,0 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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romstage-y += util.c
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ramstage-y += ramstage.c
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ramstage-y += util.c
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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29
src/mainboard/asrock/spc741d8/acpi/platform.asl
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29
src/mainboard/asrock/spc741d8/acpi/platform.asl
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@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Enable ACPI _SWS methods */
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#include <soc/intel/common/acpi/acpi_wake_source.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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/* Port 80 POST */
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OperationRegion (DBG0, SystemIO, 0x80, 0x02)
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Field (DBG0, ByteAcc, Lock, Preserve)
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{
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IO80, 8,
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IO81, 8
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}
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method (_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method (_WAK, 1)
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{
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Return (Package (){ 0, 0 })
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}
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17
src/mainboard/asrock/spc741d8/board.fmd
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17
src/mainboard/asrock/spc741d8/board.fmd
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FLASH 64M {
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SI_ALL@0x0 0x03000000 {
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SI_DESC@0x0 0x1000
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# SI_GBE@0x1000 0x2000
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# SI_ME@0x3000 0x2fed000
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SI_ME@0x1000 0x2fef000
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SI_PT@0x2ff0000 0x10000
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}
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RW_MRC_CACHE@0x3000000 0x10000
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SMMSTORE(PRESERVE) 256K
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FMAP 0x800
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RW_VPD(PRESERVE) 0x4000
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RO_VPD(PRESERVE) 0x4000
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# For CONSOLE_SPI_FLASH support
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CONSOLE 0x20000
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COREBOOT(CBFS)
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}
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7
src/mainboard/asrock/spc741d8/board_info.txt
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7
src/mainboard/asrock/spc741d8/board_info.txt
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Vendor name: ASRock Rack
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Board name: SPC741D8-2L2T/BCM
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Category: server
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ROM protocol: SPI
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ROM package: SOIC-16
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ROM socketed: y
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Flashrom support: y
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50
src/mainboard/asrock/spc741d8/bootblock.c
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50
src/mainboard/asrock/spc741d8/bootblock.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/intel/common/block/lpc/lpc_def.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6791d/nct6791d.h>
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#include <device/pnp_ops.h>
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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void bootblock_mainboard_early_init(void)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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*/
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const uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
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const uint16_t lpcioe = (LPC_IOE_EC_4E_4F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
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/* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
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/* LPC I/O enable: com1 and com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
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/* Enable com1 (0x3f8), com2 (0x2f8) and superio (0x4e) */
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pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
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pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
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/*
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* Disable the Nuvoton NCT6791D SuperIO UART1. It is enabled by
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* default, but the AST2600's is connected to the serial port.
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*/
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const pnp_devfn_t nvt_serial_dev = PNP_DEV(0x2E, NCT6791D_SP1);
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nuvoton_pnp_enter_conf_state(nvt_serial_dev);
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pnp_set_logical_device(nvt_serial_dev);
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pnp_set_enable(nvt_serial_dev, 0);
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nuvoton_pnp_exit_conf_state(nvt_serial_dev);
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/* Enable AST2600 SuperIO UART1 */
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const pnp_devfn_t ast_serial_dev = PNP_DEV(0x4E, AST2400_SUART1);
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aspeed_enable_serial(ast_serial_dev, CONFIG_TTYS0_BASE);
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}
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31
src/mainboard/asrock/spc741d8/devicetree.cb
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31
src/mainboard/asrock/spc741d8/devicetree.cb
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## SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/intel/xeon_sp/spr
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device domain 0 on
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device pci 1f.0 on # Intel device 1b81: PCH eSPI controller
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chip superio/common
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device pnp 4e.0 on
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chip superio/aspeed/ast2400
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register "use_espi" = "1"
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device pnp 4e.2 on # SUART1
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io 0x60 = 0x3f8
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irq 0x70 = 0x04
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end
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device pnp 4e.3 on # SUART2
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io 0x60 = 0x2f8
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irq 0x70 = 0x03
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end
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end
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end
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end
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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register "bmc_i2c_address" = "0x20"
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register "bmc_boot_timeout" = "60"
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end
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chip drivers/pc80/tpm # TPM
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device pnp 0c31.0 on end
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end
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end
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end
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end
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27
src/mainboard/asrock/spc741d8/dsdt.asl
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27
src/mainboard/asrock/spc741d8/dsdt.asl
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include "acpi/platform.asl"
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
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// LPC related entries
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Scope (\_SB.PC00)
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{
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#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
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}
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}
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270
src/mainboard/asrock/spc741d8/gpio.h
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270
src/mainboard/asrock/spc741d8/gpio.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CFG_GPIO_H
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#define CFG_GPIO_H
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#include <gpio.h>
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#ifndef PAD_CFG_GPIO_BIDIRECT
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#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \
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PAD_BUF(NO_DISABLE) | val, \
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PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
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#endif
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/* Pad configuration was generated automatically using intelp2m utility */
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPPC_A ------- */
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PAD_CFG_NF(GPPC_A0, NONE, RSMRST, NF1), /* ESPI_ALERT0_N */
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PAD_CFG_NF(GPPC_A1, NONE, RSMRST, NF1), /* ESPI_ALERT1_N */
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PAD_CFG_NF(GPPC_A2, NONE, RSMRST, NF1), /* ESPI_IO_0 */
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PAD_CFG_NF(GPPC_A3, NONE, RSMRST, NF1), /* ESPI_IO_1 */
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PAD_CFG_NF(GPPC_A4, NONE, RSMRST, NF1), /* ESPI_IO_2 */
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PAD_CFG_NF(GPPC_A5, NONE, RSMRST, NF1), /* ESPI_IO_3 */
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PAD_CFG_NF(GPPC_A6, NONE, RSMRST, NF1), /* ESPI_CS0_N */
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PAD_CFG_NF(GPPC_A7, NONE, RSMRST, NF1), /* ESPI_CS1_N */
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PAD_CFG_NF(GPPC_A8, NONE, RSMRST, NF1), /* ESPI_RESET_N */
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PAD_CFG_NF(GPPC_A9, NONE, RSMRST, NF1), /* ESPI_CLK */
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PAD_CFG_GPI_TRIG_OWN(GPPC_A10, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_A11, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_A12, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPPC_A13, 0, RSMRST), /* GPIO */
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PAD_NC(GPPC_A14, NONE), /* GPIO */
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PAD_NC(GPPC_A15, NONE), /* GPIO */
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PAD_CFG_GPIO_BIDIRECT(GPPC_A16, 0, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_A18, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_A19, NONE, RSMRST, OFF, ACPI), /* GPIO */
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/* ------- GPIO Group GPPC_B ------- */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B0, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B1, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B2, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B3, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B4, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_NF(GPPC_B5, NONE, RSMRST, NF1), /* USB2_OC0_N */
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PAD_CFG_NF(GPPC_B6, NONE, RSMRST, NF1), /* USB2_OC1_N */
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PAD_CFG_NF(GPPC_B7, NONE, RSMRST, NF1), /* USB2_OC2_N */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B8, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B9, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPPC_B11, 1, PLTRST), /* GPIO */
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PAD_CFG_NF(GPPC_B12, NONE, DEEP, NF4), /* 1P8_PTI_DATA5 */
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PAD_CFG_NF(GPPC_B13, NONE, DEEP, NF4), /* 1P8_PTI_DATA6 */
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PAD_CFG_NF(GPPC_B14, NONE, DEEP, NF4), /* 1P8_PTI_DATA7 */
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PAD_CFG_NF(GPPC_B15, NONE, DEEP, NF4), /* 1P8_PTI_DATA8 */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B16, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B17, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B18, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B19, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B20, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B21, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPPC_B22, 0, RSMRST), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_B23, NONE, RSMRST, OFF, ACPI), /* GPIO */
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/* ------- GPIO Group GPPC_S ------- */
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PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_NF(GPPC_S1, NONE, DEEP, NF1), /* SPRK */
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PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, RSMRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S6, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPPC_S7, NONE, RSMRST, NF1), /* SUSACK_N */
|
||||
PAD_CFG_NF(GPPC_S8, NONE, RSMRST, NF1), /* NMI_N */
|
||||
PAD_CFG_GPI_SMI(GPPC_S9, NONE, DEEP, LEVEL, INVERT), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S10, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Community 1 ------- */
|
||||
|
||||
/* ------- GPIO Group GPPC_C ------- */
|
||||
/* GPPC_C0 - RESERVED */
|
||||
/* GPPC_C1 - RESERVED */
|
||||
PAD_CFG_NF(GPPC_C2, NONE, DEEP, NF1), /* ME_SML0ALERT_N */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C4, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPO(GPPC_C5, 1, PLTRST), /* GPIO */
|
||||
/* GPPC_C6 - RESERVED */
|
||||
/* GPPC_C7 - RESERVED */
|
||||
/* GPPC_C8 - RESERVED */
|
||||
PAD_NC(GPPC_C9, NONE), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C10, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
/* GPPC_C11 - RESERVED */
|
||||
/* GPPC_C12 - RESERVED */
|
||||
/* GPPC_C13 - RESERVED */
|
||||
/* GPPC_C14 - RESERVED */
|
||||
PAD_NC(GPPC_C15, NONE), /* GPIO */
|
||||
PAD_NC(GPPC_C16, NONE), /* GPIO */
|
||||
PAD_CFG_GPO(GPPC_C17, 0, RSMRST), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C18, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C19, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C20, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_SCI(GPPC_C21, NONE, DEEP, LEVEL, INVERT), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
/* GPP_D0 - RESERVED */
|
||||
/* GPP_D1 - RESERVED */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D4, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPP_D8, NONE, RSMRST, NF1), /* CRASHLOG_TRIG_N */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPP_D11, NONE, RSMRST, NF1), /* PLTRST_N */
|
||||
PAD_CFG_NF(GPP_D12, NONE, RSMRST, NF1), /* PCHHOT_N */
|
||||
/* GPP_D13 - RESERVED */
|
||||
PAD_CFG_NF(GPP_D14, NONE, RSMRST, NF1), /* ADR_TRIGGER */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPP_D16, NONE, RSMRST, NF1), /* ADR_ACK */
|
||||
/* GPP_D17 - RESERVED */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPP_D21, NONE, RSMRST, NF1), /* GLB_RST_WARN_N */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Community 3 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_GPI_NMI(GPP_E0, NONE, PLTRST, LEVEL, INVERT), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_NF(GPP_E2, NONE, RSMRST, NF1), /* SATA1_XPCIE_2 */
|
||||
PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1), /* SATA1_XPCIE_3 */
|
||||
PAD_CFG_NF(GPP_E4, NONE, RSMRST, NF1), /* SATA0_XPCIE_2 */
|
||||
PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA0_XPCIE_1 */
|
||||
PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA0_USB3_XPCIE_0 */
|
||||
PAD_CFG_NF(GPP_E7, NONE, RSMRST, NF1), /* SATA0_USB3_XPCIE_1 */
|
||||
PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF2), /* SATA0_LED_N */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E9, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group JTAG ------- */
|
||||
|
||||
/* ------- GPIO Community 4 ------- */
|
||||
|
||||
/* ------- GPIO Group GPPC_H ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
/* GPPC_H1 - RESERVED */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H2, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H3, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H4, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H5, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H8, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H9, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H10, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H11, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H12, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H13, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H14, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPO(GPPC_H15, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPO(GPPC_H18, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), /* CPUPWRGD */
|
||||
/* GPP_J1 - RESERVED */
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), /* PLTRST_CPU_N */
|
||||
PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), /* TRIGGER0_N */
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* TRIGGER1_N */
|
||||
/* GPP_J5 - RESERVED */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
/* GPP_J8 - RESERVED */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J12, UP_20K, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J13, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J14, UP_20K, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J15, UP_20K, DEEP, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Community 5 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I1, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I2, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I3, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I11, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I12, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I13, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I14, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_L ------- */
|
||||
/* GPP_L0 - RESERVED */
|
||||
/* GPP_L1 - RESERVED */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
/* GPP_L4 - RESERVED */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_M ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M9, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M10, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M13, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M14, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_N ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_N0, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_N1, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_N2, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_N3, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_N4, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
};
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
||||
106
src/mainboard/asrock/spc741d8/include/mainboard_iio.h
Normal file
106
src/mainboard/asrock/spc741d8/include/mainboard_iio.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef _MAINBOARD_IIO_H_
|
||||
#define _MAINBOARD_IIO_H_
|
||||
|
||||
#include <defs_iio.h>
|
||||
#include <soc/soc_util.h>
|
||||
|
||||
/* For now only set 3 fields and hard-coded others, should be extended in the future */
|
||||
#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \
|
||||
{ \
|
||||
.SLOTEIP = 0, \
|
||||
.SLOTHPCAP = 0, \
|
||||
.SLOTHPSUP = 0, \
|
||||
.SLOTPIP = 0, \
|
||||
.SLOTAIP = 0, \
|
||||
.SLOTMRLSP = 0, \
|
||||
.SLOTPCP = 0, \
|
||||
.SLOTABP = 0, \
|
||||
.SLOTIMP = slotimp, \
|
||||
.SLOTSPLS = 0, \
|
||||
.SLOTSPLV = 0, \
|
||||
.SLOTPSP = slotpsp, \
|
||||
.VppEnabled = 0, \
|
||||
.VppPort = 0, \
|
||||
.VppAddress = 0, \
|
||||
.MuxAddress = 0, \
|
||||
.ChannelID = 0, \
|
||||
.PciePortEnable = 1, \
|
||||
.PEXPHIDE = pexphide, \
|
||||
.HidePEXPMenu = 0, \
|
||||
.PciePortOwnership = 0, \
|
||||
.RetimerConnectCount = 0, \
|
||||
.PcieMaxPayload = 0x7, \
|
||||
.PciePortLinkSpeed = 0, \
|
||||
.DfxDnTxPresetGen3 = 0xFF \
|
||||
}
|
||||
|
||||
#define CFG_UPD_PCIE_PORT_DISABLED CFG_UPD_PCIE_PORT(1, 0, 0)
|
||||
|
||||
/*
|
||||
* SPC741D8-2L2T IIO PCIe Port Table
|
||||
*/
|
||||
static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY iio_pci_port[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = {
|
||||
{
|
||||
/* DMI port: array index 0 */
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0),
|
||||
/* IOU0 (PE0): array index 1 ~ 8 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU1 (PE1): array index 9 ~ 16 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU2 (PE2): array index 17 ~ 24 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU3 (PE3): array index 25 ~ 32 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU4 (PE4): array index 33 ~ 40 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT(0, 1, 37), /* 59:05.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
},
|
||||
};
|
||||
|
||||
static const UINT8 iio_bifur[CONFIG_MAX_SOCKET][5] = {
|
||||
// Note: When changing, also update port configurations above.
|
||||
{
|
||||
IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE3 */
|
||||
IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE5 */
|
||||
IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE1 (farthest from CPU) */
|
||||
IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE7 (closest to CPU) */
|
||||
IIO_BIFURCATE_xxx8xxx8, /* MCIO */
|
||||
},
|
||||
};
|
||||
#endif /* _MAINBOARD_IIO_H_ */
|
||||
42
src/mainboard/asrock/spc741d8/ramstage.c
Normal file
42
src/mainboard/asrock/spc741d8/ramstage.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/smmrelocate.h>
|
||||
#include <device/i2c_simple.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSPS_UPD *params)
|
||||
{
|
||||
/* configure Emmitsburg PCH GPIO controller after FSP-M */
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
||||
void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
|
||||
{
|
||||
soc_ubox_store_resources(slots, size);
|
||||
}
|
||||
|
||||
void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
|
||||
{
|
||||
const u8 so = dimm->soc_num;
|
||||
const u8 ch = dimm->channel_num;
|
||||
const u8 mm = dimm->dimm_num;
|
||||
|
||||
// generate locator strings matching OEM firmware (CPU1_DIMM_A1, CPU1_DIMM_B1, ..., CPU1_DIMM_H1)
|
||||
char dev_loc[40] = { "\x00" };
|
||||
snprintf(dev_loc, sizeof(dev_loc), "CPU%u_DIMM_%c%u", so + 1, 'A' + ch, mm + 1);
|
||||
t->device_locator = smbios_add_string(t->eos, dev_loc);
|
||||
|
||||
// memory controllers are numbered 0-3 (e.g. "NODE 0" used for DIMMs A1 and B1, "NODE 1" for C1 and D1, ...)
|
||||
char bnk_loc[40] = { "\x00" };
|
||||
snprintf(bnk_loc, sizeof(bnk_loc), "NODE %u", ch / 2);
|
||||
t->bank_locator = smbios_add_string(t->eos, bnk_loc);
|
||||
}
|
||||
|
||||
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count)
|
||||
{
|
||||
// GENERIC_LINEAR_FRAMEBUFFER enables I2C compilation for the Aspeed VGA controller.
|
||||
// This is not supported (or needed) on the SPC741D8, so stub the function.
|
||||
return -1;
|
||||
}
|
||||
68
src/mainboard/asrock/spc741d8/romstage.c
Normal file
68
src/mainboard/asrock/spc741d8/romstage.c
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/ocp/ewl/ocp_ewl.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <soc/ddr.h>
|
||||
#include <defs_cxl.h>
|
||||
#include <defs_iio.h>
|
||||
#include <mainboard_iio.h>
|
||||
|
||||
void mainboard_ewl_check(void)
|
||||
{
|
||||
get_ewl();
|
||||
}
|
||||
|
||||
static void mainboard_config_iio(FSPM_UPD *mupd)
|
||||
{
|
||||
/* Set socket 0 IIO PCIe PE0,PE1,PE2,PE3 to CXL mode */
|
||||
mupd->FspmConfig.IioPcieSubSystemMode0[0] = IIO_MODE_CXL;
|
||||
mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL;
|
||||
mupd->FspmConfig.IioPcieSubSystemMode2[0] = IIO_MODE_CXL;
|
||||
mupd->FspmConfig.IioPcieSubSystemMode3[0] = IIO_MODE_CXL;
|
||||
|
||||
mupd->FspmConfig.DfxCxlHeaderBypass = 0;
|
||||
mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED;
|
||||
|
||||
mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; /* ms */
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
/* Send FSP log message to main serial port */
|
||||
mupd->FspmConfig.SerialIoUartDebugEnable = 1;
|
||||
mupd->FspmConfig.SerialIoUartDebugIoBase = CONFIG_TTYS0_BASE;
|
||||
|
||||
/* Set Rank Margin Tool to disable. */
|
||||
mupd->FspmConfig.EnableRMT = 0x0;
|
||||
/* Enable - Portions of memory reference code will be skipped
|
||||
* when possible to increase boot speed on warm boots.
|
||||
* Disable - Disables this feature.
|
||||
* Auto - Sets it to the MRC default setting.
|
||||
*/
|
||||
mupd->FspmConfig.AttemptFastBoot = 0x1;
|
||||
mupd->FspmConfig.AttemptFastBootCold = 0x1;
|
||||
|
||||
/* Set Adv MemTest Option to 0. */
|
||||
mupd->FspmConfig.AdvMemTestOptions = 0x0;
|
||||
/* Set MRC Promote Warnings to disable.
|
||||
Determines if MRC warnings are promoted to system level. */
|
||||
mupd->FspmConfig.promoteMrcWarnings = 0x0;
|
||||
/* Set Promote Warnings to disable.
|
||||
Determines if warnings are promoted to system level. */
|
||||
mupd->FspmConfig.promoteWarnings = 0x0;
|
||||
soc_config_iio(mupd, iio_pci_port, iio_bifur);
|
||||
mainboard_config_iio(mupd);
|
||||
}
|
||||
|
||||
bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
|
||||
{
|
||||
if (socket >= CONFIG_MAX_SOCKET)
|
||||
return false;
|
||||
// SPC741D8 supports 8 channels with 1 DIMM each
|
||||
if (channel >= 8)
|
||||
return false;
|
||||
if (dimm >= 1)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
10
src/mainboard/asrock/spc741d8/util.c
Normal file
10
src/mainboard/asrock/spc741d8/util.c
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/config.h>
|
||||
|
||||
#if CONFIG(SOC_INTEL_HAS_CXL)
|
||||
enum xeonsp_cxl_mode get_cxl_mode(void)
|
||||
{
|
||||
return XEONSP_CXL_SYS_MEM;
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue