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mb/hp: Add HP ProDesk 600 G1 SFF Business PC (Haswell / NPCD379 SIO)

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The HP ProDesk 600 G1 SFF comes with a mainboard named "Merlin Rev.A"
which is also used by the EliteDesk 800 G1 SFF and Z230 SFF series.
Differences are in available USB2, USB3 and SATA (headers / ports)
, PCIe (slots / length), video outputs (number / type) or chipset used.
While the EliteDesk 800 G1 SFF shares the same OEM BIOS update file, the
Z230 SFF differs. This port was made on a model with 2 DP / DP++, 1 VGA,
4 USB2 and 2 USB3 backpanel ports, 4 SATA ports and 4 PCIe slots
(1 16x and 3 1x length) using a Q85 chipset (without heat sink).

Model: HP ProDesk 600 G1 SFF Business PC
Regulatory Model: TPC-F046-SF
Product No. J0E94ET#ABH, PROMO600PDeSi54590500hq4X46k NL (C8T44AV)
Mainboard: Merlin Rev.A, 795972-001

Pure autoport (initial commit) doesn't boot, more patches will bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, devicetree edits enabled all PCIe ports and some NPCD379
code from other HP desktops makes most superio related functions work.

Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L12873F in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!

Tested:
 - coreboot 25.06-77-g812d0e2f626d as base
 - EDK2 (MrChromebox/2502)
 - SeaBIOS 1.16.3
 - Broadwell mrc.bin (tidus)
 - Haswell mrc.bin (peppy)
 - Haswell NRI
 - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
 - both DP / DP++ (HDMI) & VGA output available during POST, BOOT and OS
 - Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
 - RAM 1/2/3/4 slots filled using mixed 1.35 / 1.5v 1333 / 1600MHz DIMMs
	(NRI & mrc.bin)
	0/1: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
	0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
	1/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
	0/3: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
 - Fedora MATE 42 (Kernel 6.14)
 - KDE NEON 6.4 (Kernel 6.11)
 - MS Windows 10 / 11
 - Audio Outputs: 2x DP, Headphone, Line Out, Speaker (left&right chan.)
 - Audio Input: Line In (back)
 - USB2/3 all ports (including internal headers)
 - Intel I217-LM Gb LAN
 - SATA 4 ports
 - PCIe 16x slot @2.5GT/s (or 8x @8GT/s) and three 1x slots @5GT/s
 - dGPU nVidia GeForce GT640-2GD3 / AMD Radeon RX460 4GB (PCIe 8x)
	(disabled Hide PEG devices, option ROMs load in SeaBIOS & EDK2)
 - PS/2 ports (both Keyboard and Mouse)
 - Serial port (coreboot console & OS)
 - PowerButton (Poweron/Poweroff/Wake)
 - LEDs HDD & POWER (both off during suspend)
 - Shutdown/Reboot/Suspend
 - power_on_after_fail= Disable / Enable / Keep
 - Strip down the Intel ME/TXE firmware (make menuconfig)
 - Disabling ME HECI (manually disable in devicetree.cb)
 - flashrom -p internal -c "MX25L12835F/MX25L12873F" #(read & write)

Not tested:
 - COMB (serial port header)
 - PAR (parallel port header)
 - Audio Input Microphone Port (front)
 - USBDEBUG PORT
 - VBIOS

Not working:
 - CMOS checksum errors only on psu_fan_lvl resets to defaults sometimes
 - dual GPU (iGPU shows visual glitches while dGPU works fine)
	This occurs on both Broadwell, Haswell mrc.bin and Haswell NRI,
	may show i915 error in dmesg after waking from suspend!
	All dGPU testing have been done with a cheap PCIe riser cable!
 - Disable Intel ME PCI interface (make menuconfig)
 - PSU FAN control its either full OFF or full ON see instruction!
 - TPM Windows 10/11 detects it but "bios failed to communicate error"
 - Wake on LAN (Power on from coldboot work, but not wake from suspend)

PSU FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!

NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.

The data.vbt blob was extracted using debugfs from the OEM firmware
v2.65 enabling both Displayport / DP++ (HDMI) and VGA video outputs.

Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.

Change-Id: If1082e0b56364f32e43f954b589fa627cbaee50c
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88616
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Walter Sonius 2025-08-02 21:47:31 +02:00 • committed by Matt DeVillier
commit 4b46a0690e
17 changed files with 612 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

32
src/mainboard/hp/prodesk_600_g1_sff/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if BOARD_HP_PRODESK_600_G1_SFF
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select CPU_INTEL_HASWELL
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_HAS_TPM1
select MAINBOARD_USES_IFD_GBE_REGION
select MEMORY_MAPPED_TPM
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_NUVOTON_NPCD378
config MAINBOARD_DIR
default "hp/prodesk_600_g1_sff"
config MAINBOARD_PART_NUMBER
default "ProDesk 600 G1 SFF"
config USBDEBUG_HCD_INDEX # FIXME: check this
default 2
endif

4
src/mainboard/hp/prodesk_600_g1_sff/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_HP_PRODESK_600_G1_SFF
bool "ProDesk 600 G1 SFF"

6
src/mainboard/hp/prodesk_600_g1_sff/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

3
src/mainboard/hp/prodesk_600_g1_sff/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

10
src/mainboard/hp/prodesk_600_g1_sff/acpi/platform.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK, 1)
{
Return(Package() {0, 0})
}
Method(_PTS, 1)
{
}

3
src/mainboard/hp/prodesk_600_g1_sff/acpi/superio.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/pc80/pc/ps2_controller.asl>

8
src/mainboard/hp/prodesk_600_g1_sff/board_info.txt Normal file
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Category: desktop
Board URL: https://support.hp.com/us-en/product/setup-user-guides/hp-prodesk-600-g1-small-form-factor-pc/model/5387451
ROM IC: MX25L12873F
ROM protocol: SPI
Flashrom support: y
ROM package: SOIC8
ROM socketed: no
Release year: 2013

13
src/mainboard/hp/prodesk_600_g1_sff/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/pch.h>
#include <superio/nuvoton/npcd378/npcd378.h>
#include <superio/nuvoton/common/nuvoton.h>
#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
void mainboard_config_superio(void)
{
if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

7
src/mainboard/hp/prodesk_600_g1_sff/cmos.default Normal file
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## SPDX-License-Identifier: GPL-2.0-only
boot_option=Fallback
debug_level=Debug
nmi=Enable
power_on_after_fail=Disable
psu_fan_lvl=3

51
src/mainboard/hp/prodesk_600_g1_sff/cmos.layout Normal file
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## SPDX-License-Identifier: GPL-2.0-only
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
400 3 h 0 psu_fan_lvl
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums
checksum 392 415 984

BIN
src/mainboard/hp/prodesk_600_g1_sff/data.vbt Normal file
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Binary file not shown.

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src/mainboard/hp/prodesk_600_g1_sff/devicetree.cb Normal file
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chip northbridge/intel/haswell
register "gpu_ddi_e_connected" = "1"
register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
chip cpu/intel/haswell
device cpu_cluster 0 on ops haswell_cpu_bus_ops end
end
device domain 0 on
ops haswell_pci_domain_ops
subsystemid 0x103c 0x18e7 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # X16PCIEXP1
device pci 02.0 on end # Internal graphics VGA controller
device pci 03.0 on end # Mini-HD audio
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
register "gen1_dec" = "0x00fc0a01"
register "gen2_dec" = "0x00fc0801"
register "gpe0_en_1" = "0x0146"
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
register "sata_port_map" = "0x3f"
device pci 14.0 on end # xHCI Controller
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 on end # Management Engine KT
device pci 19.0 on end # Intel Gigabit Ethernet I217-LM
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # X1PCIEXP2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 on end # X1PCIEXP1
device pci 1c.4 on end # X1PCIEXP3
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1f.0 on # LPC bridge
chip superio/common
device pnp 2e.ff on # passes SIO base addr to SSDT gen
chip superio/nuvoton/npcd378
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel port
# global
# serialice: Vendor writes:
irq 0x14 = 0x9c
irq 0x1c = 0xa8
irq 0x1d = 0x08
irq 0x22 = 0x3f
irq 0x1a = 0xb0
# dumped from superiotool:
irq 0x1b = 0x1e
irq 0x27 = 0x08
irq 0x2a = 0x20
irq 0x2d = 0x01
# parallel port
io 0x60 = 0x378
irq 0x70 = 0x07
drq 0x74 = 0x04
end
device pnp 2e.2 off # COM1
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # COM2, IR
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 on # LED control
io 0x60 = 0x0a00
# IOBASE[0h] = bit0 LED red / green
# IOBASE[0h] = bit1-4 LED PWM duty cycle
# IOBASE[1h] = bit6 SWCC
io 0x62 = 0x0a10
# IOBASE [0h] = GPES
# IOBASE [1h] = GPEE
# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
# IOBASE [8h:bh] = GPS
# IOBASE [ch:fh] = GPE
end
device pnp 2e.5 on # Mouse
irq 0x70 = 0xc
end
device pnp 2e.6 on # Keyboard
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 0x01
# serialice: Vendor writes:
drq 0xf0 = 0x40
end
device pnp 2e.7 on # WDT ?
io 0x60 = 0x0a20
end
device pnp 2e.8 off # HWM
io 0x60 = 0x800
# IOBASE[0h:feh] HWM page
# IOBASE[ffh] bit0-bit3 page selector
drq 0xf0 = 0x20
drq 0xf1 = 0x01
drq 0xf2 = 0x40
drq 0xf3 = 0x01
drq 0xf4 = 0x66
drq 0xf5 = 0x67
drq 0xf6 = 0x66
drq 0xf7 = 0x01
end
device pnp 2e.f on # GPIO OD ?
drq 0xf1 = 0x97
drq 0xf2 = 0x01
drq 0xf5 = 0x08
drq 0xfe = 0x80
end
device pnp 2e.15 on # BUS ?
io 0x60 = 0x0a80
io 0x62 = 0x0a90
end
device pnp 2e.1c on # Suspend Control ?
io 0x60 = 0x0a40
# writing to IOBASE[5h]
# 0x0: Power off
# 0x9: Power off and bricked until CMOS battery removed
end
device pnp 2e.1e on # GPIO ?
io 0x60 = 0x0a60
drq 0xf4 = 0x01
# skip the following, as it
# looks like remapped registers
#drq 0xf5 = 0x06
#drq 0xf6 = 0x60
#drq 0xfe = 0x03
end
end
end
end
chip drivers/pc80/tpm
device pnp 4e.0 on end # TPM module
end
end
device pci 1f.2 on end # SATA Controller (AHCI)
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller (Legacy)
device pci 1f.6 off end # Thermal
end
end
end

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src/mainboard/hp/prodesk_600_g1_sff/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
}
}

19
src/mainboard/hp/prodesk_600_g1_sff/gma-mainboard.ads Normal file
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-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(DP1,
DP2,
HDMI1,
HDMI2,
Analog,
others => Disabled);
end GMA.Mainboard;

221
src/mainboard/hp/prodesk_600_g1_sff/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_NATIVE,
.gpio11 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_NATIVE,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_NATIVE,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_GPIO,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_GPIO,
.gpio26 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_NATIVE,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_OUTPUT,
.gpio3 = GPIO_DIR_OUTPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio18 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_INPUT,
.gpio26 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio2 = GPIO_LEVEL_HIGH,
.gpio3 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio24 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
.gpio1 = GPIO_INVERT,
.gpio4 = GPIO_INVERT,
.gpio5 = GPIO_INVERT,
.gpio6 = GPIO_INVERT,
.gpio7 = GPIO_INVERT,
.gpio11 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
.gpio17 = GPIO_INVERT,
.gpio19 = GPIO_INVERT,
.gpio21 = GPIO_INVERT,
.gpio22 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_GPIO,
.gpio44 = GPIO_MODE_GPIO,
.gpio45 = GPIO_MODE_GPIO,
.gpio46 = GPIO_MODE_GPIO,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_NATIVE,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_GPIO,
.gpio61 = GPIO_MODE_GPIO,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_INPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_OUTPUT,
.gpio61 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio51 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio55 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE,
.gpio65 = GPIO_MODE_NATIVE,
.gpio66 = GPIO_MODE_NATIVE,
.gpio67 = GPIO_MODE_NATIVE,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_GPIO,
.gpio74 = GPIO_MODE_GPIO,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_OUTPUT,
.gpio73 = GPIO_DIR_INPUT,
.gpio74 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio72 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

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src/mainboard/hp/prodesk_600_g1_sff/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0221, /* Codec Vendor / Device ID: Realtek */
0x103c18e7, /* Subsystem ID */
11, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x103c18e7),
AZALIA_PIN_CFG(0, 0x12, 0x403c0000),
AZALIA_PIN_CFG(0, 0x14, 0x01014020),
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1a, 0x02a1103f),
AZALIA_PIN_CFG(0, 0x1b, 0x01813030),
AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/hp/prodesk_600_g1_sff/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void)
{
}
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_FLEX },
{ 0x0040, 1, 0, USB_PORT_FLEX },
{ 0x0110, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 3, USB_PORT_FLEX },
{ 0x0040, 1, 3, USB_PORT_FLEX },
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_FLEX },
{ 0x0040, 1, 5, USB_PORT_FLEX },
{ 0x0110, 1, 7, USB_PORT_BACK_PANEL },
{ 0x0110, 1, 7, USB_PORT_BACK_PANEL },
};
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 0, 3 },
{ 0, 3 },
{ 1, 5 },
{ 1, 5 },
};