erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/nissa/var/pujjocento: Change touchpanel sequence to meet spec

Browse source 
Setup GPP_C0 and GPP_C1 in early and romstage to meet spec requirements
Spec require TP_Reset ON after VTSP ON 0-10ms.
Before modification，TP_Reset ON before VTSP ON.
After modification，TP_Reset ON after VTSP ON 1ms.

BUG=b:421455835
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence

Change-Id: I7d3d79c9f67edf42b64316757c448fe385207a86
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Zhongtian Wu 2025-08-07 15:04:05 +08:00 • committed by Subrata Banik
commit 0bedce05d8
1 changed files with 2 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/mainboard/google/brya/variants/pujjocento/gpio.c
View file

@ -102,8 +102,6 @@ static const struct pad_config gpio_table[] = {
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> TCHSCR_RST_L */
PAD_CFG_GPO(GPP_C1, 1, DEEP),
/* C2 : SMBALERT# ==> GPP_C2_STRAP */
PAD_NC(GPP_C2, NONE),
/* C3 : EN_PP3300_UCAM_X */
@ -180,6 +178,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
/* E10 : EN_PP3300_WLAN_X */
PAD_CFG_GPO(GPP_E10, 0, DEEP),
/* C1 : SMBDATA ==> TCHSCR_RST_L */
PAD_CFG_GPO(GPP_C1, 1, DEEP),
/* E11 : TCHSCR_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
@ -432,10 +432,6 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> TCHSCR_RST_L */
PAD_CFG_GPO(GPP_C1, 1, DEEP),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* E3 : PROC_GP0 ==> SOC_WP_OD */