Move the MIPI panel init command parsing function
mipi_panel_parse_init_commands() and related macros and structs from
drivers/mipi/ to commonlib/mipi/, so that the function can be shared
with payloads.
In a follow-up patch, a 'poweroff' field will be added to the
panel_serializable_data struct and then passed to payloads, so that
payloads can utilize mipi_panel_parse_init_commands() to run the panel
poweroff commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I19011669f03d060e9f030b673687cbe5965d7e2f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Increased MHBR field width in ACPI northbridge.asl from 17 to 27 bits,
allowing MCHBAR to be set above 4GB (up to 42 bits).
Reference: Section 10.3 in 850519
BUG=none
TEST=boot to OS with ACPI debug enabled and check GMHB log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I885ff64598367ddadcec05926af3556024b61250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90729
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit 14a7a2315e.
Reason for revert: The change causes DUT failed to resume from S3.
BUG=b:474254985
TEST=Wake up DUT by power key.
Change-Id: I2f2291a12d9b440d000a28e38bb590bc77a02c8a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The number of MCAX register used inside an MCA BANK changed from phoenix
onwards. Since phoenix all 16 MCAX register are used inside an MCA bank.
According to spec:
The MCA_SYND register stores a syndrome associated with the error logged
in MCA_STATUS or MCA_DESTAT. The “syndrome” may include syndrome values
associated with an error correcting code or other information about the
error. The contents of this register are valid if MCA_STATUS[SYNDV] bit
is set to 1 or MCA_DESTAT[SYNDV] bit is set to 1.
source: AMD64 Architecture Programmers Manual Rev 3.42
Change-Id: I20a31776d4b031c810ef0dc6502c421ade6f4315
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the SoC USB driver to invoke mainboard_usb_typec_configure for
both primary and secondary ports. This is called after the QMP PHY
initialization to ensure the external signal path is correctly
muxed for the detected orientation.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 00001203 00000000 00000000 00000000 ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000 ................
0a600430: 00001203 00000000 00000000 00000000 ................
```
Change-Id: Ic90a62b1f6ad62a8870c6d5333d06b6a11d26d4f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90711
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add a function declaration for mainboard_usb_typec_configure. This
allows mainboards to implement custom logic for external components,
such as retimers or muxes, that need orientation-aware configuration.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Change-Id: I20d9a23da5b855a413f8358b8783f44c1632ccdf
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90709
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add spinlock synchronization to prevent concurrent SPI flash controller
access from multiple CPUs in SMP environments. The spinlock serializes
access to the SPI controller hardware in exec_sync_hwseq_xfer().
If SMP is not enabled, spinlock functions are no-ops, so this change
is safe for both SMP and non-SMP configurations.
This resolves an issue seen on the Starlabs Starfighter MTL where
multiple SPI transaction errors occurred when reading option variables
stored in SMMSTORE:
[ERROR] SPI Transaction Error at Flash Offset 103002a HSFSTS = 0x01016022
[ERROR] SPI Transaction Error at Flash Offset 1030004 HSFSTS = 0x01006022
[ERROR] SPI Transaction Error at Flash Offset 1030000 HSFSTS = 0x3f006022
...
Change-Id: Ic3003b0a986b587622102b6f36714bcb16c3d976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Refactor code to use less redundant PCI accesses to decrease boot time.
Change-Id: Ic2bb610ebf22dd43580ac94360d905b1c782224a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90641
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor fsp_init to be called as a boot state entry
(BS_DEV_INIT, BS_ON_ENTRY) instead of directly from soc_init. This
ensures fsp initialization occurs at the appropriate boot stage.
This change is necessary for FW logo rendering in the ramstage. fsp_init
must be run before FW display starts rendering the logo.
BUG=b:471111147
TEST=Check FW logo
Change-Id: I41b32229d4c582d84afac5c336eb98b1b1274ba8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Starting with Turin there are 8 IOHCs per SoC. Add new definitions
for the missing IOHCs. Based on Turin C1 PPR (doc 57238).
Change-Id: I31e93e680e3f0ba03d2595f632d6827b4e3042b8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90368
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Strip quotes from CONFIG_AMDFW_CONFIG_FILE, otherwise the IF condition
may not catch the case when CONFIG_AMDFW_CONFIG_FILE is an empty string.
TEST=Omit PSP blobs when building coreboot for Gigabyte MZ33-AR1 by
clearing the AMDFW_CONFIG_FILE path.
Change-Id: I1ecf61844c03c89b3429e23936172f79c8d4b2f4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90367
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add PCI I/O-based SMN accessors. These accessors can be used for
early workarounds when the PCI ECAM MMCONF is not working yet.
An example of such workaround is the patching of PCI ECAM MMCONF
base address in Turin SoC, which has to be done via SMN, but it
cannot use PCI ECAM MMCONF to access SMN yet.
Change-Id: I5e0faaa48e4d7b4479e3af9b795ad2a879f569fd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add API to initialize RPMh resources for display. It includes CMD-DB
initialization, enable the MMCX power rail and cast a vote for the MM0
Bus Clock Manager (BCM) resource to enable display clocks.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified MMCX rail enablement and MM0 BCM vote using ARC and
BCM AOP dump with API invoking changes hooked up with follow-on
commits.
Serial Log:
[INFO ] RPMH_REG: Initialized mmcx.lvl at addr=0x30080
[INFO ] ARC regulator initialized successfully
[DEBUG] RPMH_REG: Sent active request for mmcx.lvl
[INFO ] ARC level was set successfully
[DEBUG] BCM: Found address 0x00050024 for resource MM0
[INFO ] BCM: Successfully voted for MM0 (addr=0x00050024, val=0x60004001)
[INFO ] BCM vote for MM0 sent successfully
Change-Id: I1997ce7a1ced4504d6a3170e5f2ddd4f52e0763d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90467
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add RPMh driver support, introducing the core driver that provides
an interface to the RPMh protocol for managing ARC/VRM/BCM type
resource requests. This includes basic TCS (Trigger Command Sets)
handling and helper functions for sending RPMh requests.
RPMh (Resource Power Manager – hardware) is a protocol that enables
processors (e.g., APSS, LPASS) to send power-related commands to the
RPMh hardware block. Dynamic management of power and clocks for shared
resources is handled either directly by hardware or by RPM.
Key features include:
- Core infrastructure for submitting TCS (Trigger Command Sets)
commands to the RPMh.
- Regulator driver using RPMh for LDOs and SMPS control.
- BCM (Bus Clock Manager) voting for clock resources.
Test=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I1f85459c68d0256e15765b0716856dc928080df9
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The display buffer reservation logic has been removed, so the related
symbol declarations are no longer needed.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I873fdcff4071e0d2cf683017557abdfdb13e8b16
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90653
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The display buffer was previously reserved as unavailable by coreboot,
which prevented the kernel from mapping it. When the splash driver
released the buffer, the kernel later crashed on access because the
region was never mapped.
This patch removes the reservation so the kernel can map the display
buffer and reuse it safely.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Check that the display memory region is mapped by kernel in UART logs:
[ 0.000000][ T0] node 0: [mem 0x00000000e36a0000-
0x00000000f7bfffff]
Change-Id: I507d48713690bac3030f81a29c7e123fd3a03b95
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
QCLib passes SHRM metadata to TME for authentication and to bring SHRM
out of reset. In RAM dump mode, this sequence is unnecessary because
the system is preserving state for post-crash analysis.
This patch adds a RAM-dump-mode check and ensures:
- SHRM metadata is not loaded or populated into the interface table
when RAM dump mode is detected, preventing QCLib from sending it to
TME.
Test=Create an image.serial.bin and verify it boots on X1P42100.
Change-Id: I921a2b99543ee462433bec8e8471ad836cabc5dd
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90652
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This power resource is valid in S5, so correct the level that is
set. This makes it match the reference code, and the CNVi Bluetooth
power resource.
Change-Id: I430cafafc0326dc189a337bf2b67cf200afc4f17
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90610
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current code left Bluetooth disabled if it times out during reset.
Following the flow of the reference code, re-enable it to avoid it
ending up "stuck" off.
Change-Id: Ib1c49f28ec13068d9d7e59841ae35d1d26c30770
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90607
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The saved error values were reversed, so correct these.
This isn't a functional change, as the value isn't used in ACPI.
Change-Id: I9d3abcb4b17c36d33f2660e5d20fd5e6fb15fc34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the value of BIAS_POWER_ON in the MT8189 dptx_reg.h file,
by changing it from 0x01 to 0x03. The MT8189 needs to enable one
more power register bit to make bias work rather than timeout.
BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: I345b23af0b5802e71d6d7bcd3fe806aaa71cc3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit introduces ChromeOS-specific logic to the Panther Lake SoC
TDP selection. It addresses the need to correctly set the CPU TDP to 15
W without having to set the desired_tdp flag in each mainboard device
tree.
BUG=b:465698900
Change-Id: Ibaee530159f7e3b94aac16ab50b749cb161cee10
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a mechanism to configure the Thermal Design Power
(TDP) for Panther Lake, allowing board designers to override the default
TDP reported by hardware and select the value that matches their
specific board requirements.
Previously, the TDP value was determined solely by the hardware, which
limited flexibility for platforms that support multiple TDP options. By
adding a new field to the `soc_intel_pantherlake_config` structure and
implementing the `soc_get_cpu_tdp()` function, this change enables
boards to opt out of the default TDP and specify a custom value.
BUG=b:465698900
Change-Id: I6e401c2c7d7d0cda24fa07ec024813874fac3ed5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90150
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update PL1 override values from a fixed value to zero, indicating that
the platform should use the default TDP value. This change allows the
common code to dynamically set PL1 according to the specific TDP SKU,
improving flexibility and ensuring correct power limit configuration
across different hardware variants.
Previously, PL1 was hardcoded to 15 for some SKUs, which could lead to
instabilities for SKUs with different TDP requirements.
TEST=No instability was observed on certain Fatcat SKUs.
Change-Id: Ibfb6b52aa15ad66740abc39f6f869dfa5e90de3c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89934
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Ryu, Jamie M <jamie.m.ryu@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
The pic_width and pic_height in the dsc_config struct are equivalent to
edid.mode.ha and edid.mode.va. The duplicate information should be
removed from the panel_serializable_data struct, by removing from
dsc_config. To do that, replace references of dsc_config.pic_width with
edid.mode.ha in the MT8196 code.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: Id1014886851a999ccdfec7ec86df2e7341ba9ffd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90560
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
We'd like to replace dsc_cfg->pic_width with edid->mode.ha in MT8196's
dsc_configure_registers() and then deprecate the 'pic_width' field. To
do that, we will first need to pass the edid struct pointer from
mtk_ddp_mode_set() all the way to that function.
Currently mtk_ddp_mode_set() is in the MediaTek common code, which calls
SoC's mtk_ddp_soc_mode_set(), but the edid isn't passed. To simplify the
edid pointer passing, drop mtk_ddp_soc_mode_set() and replace it with
SoC's mtk_ddp_mode_set(). To minimize the duplicate code of calculating
vrefresh, introduce mtk_get_vrefresh() to the display API, and reference
it from SoC's code.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: Ifb84c6b954dde2f25c3ac491a5392b7725c13a43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90559
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Pass dsi_regs to mtk_dsi_cphy_timing() to be consistent with other DSI
APIs and mtk_dsi_dphy_timing(). This also supports C-PHY with dual
channel, although there is currently no such a device.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: I81805aa181c46fb29c70d18553dbf0c0c06c2888
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90558
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Move dpm_init() and spm_init() from mainboard_init() in rauru to
soc_init() in mt8196. This centralizes the power management
initialization within the SoC-specific code.
BUG=none
TEST=Build pass, boot ok.
Change-Id: Ic2914fd0fc85032c96ce076416e9b9c46fe19e0d
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90550
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The mtk_ddp_ovlsys_start function is updated to take edid and path
as arguments. This allows the function to configure the framebuffer
address and overlay for DISP_PATH_DUAL_MIPI path.
BUG=b:319511268
TEST=cherry pick CB:90504 and manual enable BMP_LOGO related configs.
The logo is drawn in the ramstage.
Change-Id: I60809f7062907617f2af1badcad9f53477911020
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add an option to lock the regions BOOTBLOCK and COREBOOT, leaving the
regions TOPSWAP and COREBOOT_TS for updates in an Intel Top Swap
redundancy scenario.
This means that the user can now write and choose to boot from the
update regions, selecting the attempt_slot_b CMOS option, and there is
a protected golden copy of the entire firmware, that cannot be
overwritten and can be reverted to by resetting CMOS.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: Ia6dea22c41e2fc778af6ca7049b72c92686ec85f
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Before CPU resume, it is necessary to reinitialize the MTE-related
settings of booker in MCUPM to prevent the loss of booker
configurations after resume.
BUG=b:467186613
TEST=Build pass, Verify S/R OK on Navi and Sapphire.
Change-Id: Ieaf4c2ea0f8a5c372a5dbf4d0f6c44fbd978e6a6
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90546
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.
Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.
Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FWTS complains on HPET base not being found in DSDT/SSDT:
Test 3 of 4: Test HPET base in DSDT and/or SSDT.
WARNING: Test 3, Test skipped because HPET Device address was not
found in DSDT/SSDT.
Declare HPET device under LPC device to fix the issue.
TEST=Run FWTS on Gigabyte MZ33-AR1 and see no error in HPET tests.
Change-Id: I68b872291dc93320e7a0b33a79e3336e1372b178
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89924
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and
40h have a second 64bit EFR value that should be filled with IOMMU MMIO
offset 0x1A0 register value if EFR is supported.
[1] https://docs.amd.com/v/u/en-US/48882_IOMMU
Change-Id: I0da79bed8994671c651328cd7a29d9480a122528
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
non-cacheable
Add support to split the dram_aop memory region into three in order to
map dram_aop_cmd_db as non-cacheable. The purpose of dram_aop_config
is memory region where the aop_devcfg.mbn image is loaded.
Test=1. Build and boot on X1P42100.
2. Dump the MMU table in coreboot ramstage and verify whether the region
is mapped as non-cacheable.
Change-Id: Id73d878b7d343f248a845bd5727c43e22c4c348a
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90521
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to map AOP CMD-DB region as uncached region in MMU. The
reason for this change is that the CMD-DB region is configured as
read-only region and any write to this region will be treated as
fatal. Mapping it as cacheable can lead to cache-line writebacks,
causing invalid accesses and device crashes.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
MMU Table dump from Trace32:
'M:0000000081C60000--0000000081C7FFFF| AM:0000000081C60000--0000000081C7FFFF| s | | 00001000| read/write access exec | yes| inn| non-cacheable | 1| no | \\ramstage\Global\_dram_aop_cmd_db'
Change-Id: I296b505f670f3be28eb998fdac8164a85bf757b0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Define the QCLIB_GA_ENABLE_PD_NEGOTIATION bit in the QcLib global
attributes. This flag signals to QcLib that Power Delivery
negotiation should be performed.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.
Change-Id: Ia046f68ebeacaa1c1d9a73c4b957315c9f7b68b6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90512
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a weak function qclib_mainboard_override to allow
mainboards to customize QcLib policies or global attributes.
This hook is called from the SoC-specific QcLib initialization
path.
BUG=b:457566143
TEST=Configure QcLib policy for Google/Quenbi.
Change-Id: I0397b7138db260973ea86852cfa9f408e14d195d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure that existing flags in global_attributes are not overwritten
when enabling UART logging. Using a bitwise OR preserves any
previously set attributes.
BUG=b:457566143
TEST=Verify the QcLib global attributes.
With this CL -
```
[DEBUG] Global Attributes[0x3]..Table Entries Count[8]
```
Change-Id: Iffceb06cb800ba4c9e5c07381745cbed1fb7d550
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the SSRAM memory layout in memlayout.ld to reserve
space for several new regions.
The following regions are added to the SSRAM section:
- qsee: 100K at 0x14680000
- qdss_usb_trace: 8K at 0x146A6000
- aop_imem: 8K at 0x146A8000
The memory map diagram in the comments is also updated to reflect the
reservation of aop_imem and qdss_usb_trace.
BUG=b:456953373
TEST=Able to build and boot google/quenbih.
Change-Id: I17c2a97d31cdcb81ffdd0c83d8c6d19b9a03a91b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90443
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Relocate the PRERAM_STACK region to a new address to resolve a memory
conflict with the QSEE Trust Zone environment.
Details:
- The previous location of the PRERAM_STACK starting at 0x14680000 in
SSRAM is now reserved for QC QSEE.
- This change moves the 16KB PRERAM_STACK from 0x14680000 (SSRAM) to
the available memory region starting at 0x14850000 in the BSRAM.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: Ifa9bc457e28b9ec21aa59c6ab9114993f23b2bc8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the newly introduced PRERAM_STACK and POSTRAM_STACK macros in
the x1p42100 memory layout, addressing the memory constraints on this
SoC.
Changes
- Pre-RAM Stack: The temporary stack used before DRAM is ready is
defined using PRERAM_STACK(0x14680000, 16K) in the SSRAM region,
replacing the old generic STACK definition.
- Post-RAM Stack: The final stack is defined using
POSTRAM_STACK(0x80000000, 16K) at the start of DRAM.
- The POSTRAM_DMA_COHERENT region is shifted up to 0x80004000 to
accommodate the new 16KB post-RAM stack, avoiding memory overlap.
This guarantees a distinct and properly sized stack region for each
stage of the boot process, resolving conflicts with Trust Zone and
ensuring a clean stack transition during the RAM stage.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
w/o this patch
```
[SPEW ] stack: top_of_stack address is 0x14684000
```
w/ this patch
```
[SPEW ] stack: top_of_stack address is 0x80004000
```
Change-Id: Iccf3f99aff31a8e44386ea52b2196b49797caa79
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90405
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
