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acpi/ivrs: Fill second EFR image value

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Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and
40h have a second 64bit EFR value that should be filled with IOMMU MMIO
offset 0x1A0 register value if EFR is supported.

[1] https://docs.amd.com/v/u/en-US/48882_IOMMU

Change-Id: I0da79bed8994671c651328cd7a29d9480a122528
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
Michał Żygowski 2025-09-16 09:24:20 +02:00 • committed by Matt DeVillier
commit 0a867b3971
3 changed files with 8 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/include/acpi/acpi.h
View file

@ -595,7 +595,8 @@ typedef struct acpi_ivrs_ivhd_11 {
struct ivhd11_iommu_attr iommu_attributes;
uint32_t efr_reg_image_low;
uint32_t efr_reg_image_high;
uint32_t reserved[2];
uint32_t efr_reg_image2_low;
uint32_t efr_reg_image2_high;
uint8_t entry[];
} __packed acpi_ivrs_ivhd11_t;

3
src/include/acpi/acpi_ivrs.h
View file

@ -200,7 +200,8 @@ typedef struct acpi_ivrs_ivhd_40 {
uint32_t iommu_attributes;
uint32_t efr_reg_image_low;
uint32_t efr_reg_image_high;
uint32_t reserved[2];
uint32_t efr_reg_image2_low;
uint32_t efr_reg_image2_high;
uint8_t entry[];
} __packed acpi_ivrs_ivhd40_t;

4
src/soc/amd/common/block/acpi/ivrs.c
View file

@ -223,6 +223,8 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i
if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) {
ivhd_40->efr_reg_image_low = read32p(ivhd_40->iommu_base_low + 0x30);
ivhd_40->efr_reg_image_high = read32p(ivhd_40->iommu_base_low + 0x34);
ivhd_40->efr_reg_image2_low = read32p(ivhd_40->iommu_base_low + 0x1a0);
ivhd_40->efr_reg_image2_high = read32p(ivhd_40->iommu_base_low + 0x1a4);
}
current += sizeof(acpi_ivrs_ivhd40_t);
@ -282,6 +284,8 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i
if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) {
ivhd_11->efr_reg_image_low = read32p(ivhd_11->iommu_base_low + 0x30);
ivhd_11->efr_reg_image_high = read32p(ivhd_11->iommu_base_low + 0x34);
ivhd_11->efr_reg_image2_low = read32p(ivhd_11->iommu_base_low + 0x1a0);
ivhd_11->efr_reg_image2_high = read32p(ivhd_11->iommu_base_low + 0x1a4);
}
current += sizeof(acpi_ivrs_ivhd11_t);