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soc/qualcomm/x1p42100: Call mainboard Type-C config hook

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Update the SoC USB driver to invoke mainboard_usb_typec_configure for
both primary and secondary ports. This is called after the QMP PHY
initialization to ensure the external signal path is correctly
muxed for the detected orientation.

BUG=b:473489095
TEST=Verify USB SS detection on Quartz.

Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000    ................
0a800430: 00001203 00000000 00000000 00000000    ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000    ................
0a600430: 00001203 00000000 00000000 00000000    ................
```

Change-Id: Ic90a62b1f6ad62a8870c6d5333d06b6a11d26d4f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90711
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal 2026-01-09 13:28:53 +05:30 • committed by Subrata Banik
commit e303357cb9
1 changed files with 6 additions and 2 deletions
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8
src/soc/qualcomm/x1p42100/usb/usb.c
View file

@ -581,7 +581,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
clock_reset_bcr(dwc3->gcc_usb4_0_dp0_phy_prim_bcr, 0);
udelay(10);
/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration */
int ss0_ret = qmp_usb4_dp_phy_ss_init(0, get_usb_typec_polarity(&prim_config));
bool polarity_prim = get_usb_typec_polarity(&prim_config);
int ss0_ret = qmp_usb4_dp_phy_ss_init(0, polarity_prim);
if (ss0_ret != CB_SUCCESS) {
printk(BIOS_ERR, "SS0 QMP PHY initialization failed\n");
high_speed_only_primary = true;
@ -590,6 +591,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
enable_vbus_ss(&prim_config);
udelay(50);
usb_typec_status_check(&prim_config);
mainboard_usb_typec_configure(0, polarity_prim);
/* Type C port 1 - C1 */
/* Reset USB secondary[C1] PHY BCRs */
@ -610,7 +612,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
clock_reset_bcr(dwc3->gcc_usb4_1_dp0_phy_sec_bcr, 0);
udelay(10);
/* Initialize USB4/USB3 EDP_DP_Con PHY Configuration (secondary) */
int ss1_ret = qmp_usb4_dp_phy_ss_init(1, get_usb_typec_polarity(&sec_config));
bool polarity_sec = get_usb_typec_polarity(&sec_config);
int ss1_ret = qmp_usb4_dp_phy_ss_init(1, polarity_sec);
if (ss1_ret != CB_SUCCESS) {
printk(BIOS_ERR, "SS1 QMP PHY initialization failed\n");
high_speed_only_secondary = true;
@ -619,6 +622,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
enable_vbus_ss(&sec_config);
udelay(50);
usb_typec_status_check(&sec_config);
mainboard_usb_typec_configure(1, polarity_sec);
/* Initialize USB Controller for Type A */
setup_dwc3(dwc3->usb_host_dwc3);