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soc/mediatek/mt8196: Correct MIPI register control

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Configuring pll_con1 is wrong. Change it to voltage_sel.

BUG=b:424782827
TEST=Build pass, boot ok.
Verify display output on the following platforms:
- 8196 Navi: eDP path.
- 8189 Skywalker: eDP path.
- 8189 Padme: single MIPI path (without DSC).
- 8196 Sapphire: dual MIPI path (with DSC).

Change-Id: I300af87f3b7850cb994bc01c0572279ba18efac0
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90557
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Payne Lin 2025-12-19 15:38:38 +08:00 • committed by Yidi Lin
commit 188cd88ac7
1 changed files with 2 additions and 2 deletions
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4
src/soc/mediatek/mt8196/dsi.c
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@ -19,10 +19,10 @@ void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, u32 data_rate,
/* Select different voltage when different data rate */
if (data_rate < (u32)2500 * MHz) {
clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_MINI);
clrsetbits32(&mipi_tx_reg->voltage_sel, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_MINI);
write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF00F0);
} else {
clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_DEF);
clrsetbits32(&mipi_tx_reg->voltage_sel, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_DEF);
write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF0030);
}