soc/mediatek: Correct BIAS_ON value to get bias ready

Fix the value of BIAS_POWER_ON in the MT8189 dptx_reg.h file,
by changing it from 0x01 to 0x03. The MT8189 needs to enable one
more power register bit to make bias work rather than timeout.

BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker

Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: I345b23af0b5802e71d6d7bcd3fe806aaa71cc3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>

src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h

@@ -157,7 +157,6 @@
 #define REG_3F44_DP_ENC_4P_3				0x3F44
 #define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3			BIT(2)
 #define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK		BIT(2)
-#define BIAS_POWER_ON					(0x01 << 3)
 #define PHY_PWR_STATE_OW_VALUE_DP_ENC_4P_3_MASK		GENMASK(4, 3)
 #define REG_3F80_DP_ENC_4P_3				0x3F80
 #define PSR_PATGEN_AVT_EN_FLDMASK			0x20

src/soc/mediatek/mt8189/include/soc/dptx_reg.h

@@ -5,6 +5,7 @@
 
 #include <soc/dptx_reg_v2.h>
 
+#define BIAS_POWER_ON				(0x03 << 3)
 #define DP_PHY_DIG_TX_CTL_0			0x1444
 #define RGS_AUX_LDO_EN_READY_MASK		BIT(0)
 #define DRIVING_FORCE				0x18

src/soc/mediatek/mt8196/include/soc/dptx_reg.h

@@ -5,6 +5,7 @@
 
 #include <soc/dptx_reg_v2.h>
 
+#define BIAS_POWER_ON					(0x01 << 3)
 #define DP_PHY_DIG_TX_CTL_0				0x1474
 #define RGS_AUX_LDO_EN_READY_MASK			BIT(1)
 #define DRIVING_FORCE					0x30