soc/intel/pantherlake: Add configurable TDP support

This commit introduces a mechanism to configure the Thermal Design Power
(TDP) for Panther Lake, allowing board designers to override the default
TDP reported by hardware and select the value that matches their
specific board requirements.

Previously, the TDP value was determined solely by the hardware, which
limited flexibility for platforms that support multiple TDP options. By
adding a new field to the `soc_intel_pantherlake_config` structure and
implementing the `soc_get_cpu_tdp()` function, this change enables
boards to opt out of the default TDP and specify a custom value.

BUG=b:465698900

Change-Id: I6e401c2c7d7d0cda24fa07ec024813874fac3ed5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90150
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/pantherlake/Makefile.mk

@@ -24,6 +24,7 @@ romstage-y += espi.c
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
 romstage-y += reset.c
+romstage-y += tdp.c
 
 ramstage-y += acpi.c
 ramstage-y += cbfs_preload.c
@@ -43,6 +44,7 @@ ramstage-y += retimer.c
 ramstage-y += soundwire.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c
+ramstage-y += tdp.c
 ramstage-y += xhci.c
 ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c
 

src/soc/intel/pantherlake/chip.h

@@ -485,6 +485,15 @@ struct soc_intel_pantherlake_config {
 	uint16_t ps2_threshold[NUM_VR_DOMAINS];
 	uint16_t ps3_threshold[NUM_VR_DOMAINS];
 
+	/*
+	 * Thermal Design Power setting.
+	 *
+	 * Certain Panther Lake SKUs are compatible with multiple TDP options. For these
+	 * SKUs, the following field can be set to choose the TDP that best fits the
+	 * board's power and thermal requirements.
+	 */
+	enum soc_intel_pantherlake_cpu_tdps tdp;
+
 	/*
 	 * SerialIO device mode selection:
 	 * PchSerialIoDisabled,

src/soc/intel/pantherlake/romstage/fsp_params.c

@@ -14,6 +14,7 @@
 #include <soc/msr.h>
 #include <soc/pcie.h>
 #include <soc/romstage.h>
+#include <tdp.h>
 #include <static.h>
 
 #include "ux.h"
@@ -321,7 +322,7 @@ static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_in
 		return NULL;
 	}
 
-	uint8_t tdp = get_cpu_tdp();
+	enum soc_intel_pantherlake_cpu_tdps tdp = soc_get_cpu_tdp();
 	for (size_t i = 0; i < ARRAY_SIZE(cpuid_to_ptl); i++) {
 		const struct soc_intel_pantherlake_power_map *current = &cpuid_to_ptl[i];
 		if (current->cpu_id == sa_pci_id && current->cpu_tdp == tdp)

src/soc/intel/pantherlake/systemagent.c

@@ -16,6 +16,7 @@
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 #include <static.h>
+#include <tdp.h>
 
 /*
  * SoC implementation
@@ -145,7 +146,7 @@ static void configure_tdp(struct device *dev)
 	struct soc_power_limits_config *soc_config;
 	struct device *sa;
 	uint16_t sa_pci_id;
-	u8 tdp;
+	enum soc_intel_pantherlake_cpu_tdps tdp;
 	size_t i;
 	bool config_tdp = false;
 	struct soc_intel_pantherlake_config *config;
@@ -161,7 +162,7 @@ static void configure_tdp(struct device *dev)
 		return;
 	}
 
-	tdp = get_cpu_tdp();
+	tdp = soc_get_cpu_tdp();
 
 	/*
 	 * Choose power limits configuration based on the CPU SA PCI ID and
@@ -174,6 +175,7 @@ static void configure_tdp(struct device *dev)
 			if (config->enable_fast_vmode[VR_DOMAIN_IA] &&
 			    soc_config->tdp_pl4_fastvmode)
 				soc_config->tdp_pl4 = soc_config->tdp_pl4_fastvmode;
+			soc_config->tdp_pl1_override = tdp;
 			set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 			config_tdp = true;
 			printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n",

src/soc/intel/pantherlake/tdp.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci.h>
+#include <soc/pci_devs.h>
+#include <static.h>
+#include <tdp.h>
+
+enum soc_intel_pantherlake_cpu_tdps soc_get_cpu_tdp(void)
+{
+	const struct soc_intel_pantherlake_config *config = config_of_soc();
+	return config->tdp || get_cpu_tdp();
+}

src/soc/intel/pantherlake/tdp.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_TDP_H_
+#define _SOC_PANTHERLAKE_TDP_H_
+
+#include <chip.h>
+
+enum soc_intel_pantherlake_cpu_tdps soc_get_cpu_tdp(void);
+
+#endif /* _SOC_PANTHERLAKE_TDP_H_ */