soc/mediatek/common: Pass dsi_regs to mtk_dsi_cphy_timing()

Pass dsi_regs to mtk_dsi_cphy_timing() to be consistent with other DSI
APIs and mtk_dsi_dphy_timing(). This also supports C-PHY with dual
channel, although there is currently no such a device.

BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none

Change-Id: I81805aa181c46fb29c70d18553dbf0c0c06c2888
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90558
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>

src/soc/mediatek/common/dsi_common.c

@@ -481,8 +481,7 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		mtk_dsi_reset(dsi);
 		struct mtk_phy_timing phy_timing = {};
 		if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
-			/* Dual channel is not implemented for CPHY. */
-			mtk_dsi_cphy_timing(data_rate, &phy_timing);
+			mtk_dsi_cphy_timing(dsi, data_rate, &phy_timing);
 		else
 			mtk_dsi_dphy_timing(dsi, data_rate, &phy_timing);
 

src/soc/mediatek/common/include/soc/dsi_common.h

@@ -174,7 +174,8 @@ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
 void mtk_dsi_cphy_enable(struct mipi_tx_regs *mipi_tx_reg);
 void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg);
 void mtk_dsi_cphy_lane_sel_setting(struct mipi_tx_regs *mipi_tx_reg);
-void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing);
+void mtk_dsi_cphy_timing(struct dsi_regs *dsi_reg, u32 data_rate,
+			 struct mtk_phy_timing *timing);
 void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
 			     const struct mtk_phy_timing *phy_timing,
 			     const u32 bytes_per_pixel, const u32 hbp, const u32 hfp,

src/soc/mediatek/common/mtk_mipi_cphy.c

@@ -42,7 +42,8 @@ void mtk_dsi_cphy_enable_cmdq_6byte(struct dsi_regs *dsi_reg)
 	clrbits32(&dsi_reg->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN);
 }
 
-void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
+void mtk_dsi_cphy_timing(struct dsi_regs *dsi_reg, u32 data_rate,
+			 struct mtk_phy_timing *timing)
 {
 	u32 cycle_time, value;
 
@@ -72,14 +73,14 @@ void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
 
 	value = timing->lpx | timing->da_hs_prepare << 8 |
 		  timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
-	write32(&dsi0->dsi_phy_timecon0, value);
+	write32(&dsi_reg->dsi_phy_timecon0, value);
 
 	value = timing->ta_go | timing->ta_sure << 8 |
 		  timing->ta_get << 16 | timing->da_hs_exit << 24;
-	write32(&dsi0->dsi_phy_timecon1, value);
+	write32(&dsi_reg->dsi_phy_timecon1, value);
 
-	write32(&dsi0->dsi_cphy_con0, 0x012C0003);
-	write32(&dsi0->dsi_bllp_wc, 16 * 3);
+	write32(&dsi_reg->dsi_cphy_con0, 0x012C0003);
+	write32(&dsi_reg->dsi_bllp_wc, 16 * 3);
 }
 
 void mtk_dsi_cphy_vdo_timing(const u32 lanes,