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soc/qc/x1p42100: Define pre- & post-RAM stack regions in linker script

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Implement the newly introduced PRERAM_STACK and POSTRAM_STACK macros in
the x1p42100 memory layout, addressing the memory constraints on this
SoC.

Changes
 - Pre-RAM Stack: The temporary stack used before DRAM is ready is
   defined using PRERAM_STACK(0x14680000, 16K) in the SSRAM region,
   replacing the old generic STACK definition.

 - Post-RAM Stack: The final stack is defined using
   POSTRAM_STACK(0x80000000, 16K) at the start of DRAM.

 - The POSTRAM_DMA_COHERENT region is shifted up to 0x80004000 to
   accommodate the new 16KB post-RAM stack, avoiding memory overlap.

This guarantees a distinct and properly sized stack region for each
stage of the boot process, resolving conflicts with Trust Zone and
ensuring a clean stack transition during the RAM stage.

BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.

w/o this patch

```
[SPEW ]  stack: top_of_stack address is 0x14684000
```

w/ this patch

```
[SPEW ]  stack: top_of_stack address is 0x80004000
```

Change-Id: Iccf3f99aff31a8e44386ea52b2196b49797caa79
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90405
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2025-12-06 19:38:13 +00:00
commit a26b718d5a
1 changed files with 7 additions and 4 deletions
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11
src/soc/qualcomm/x1p42100/memlayout.ld
View file

@ -85,7 +85,9 @@
* 0x80E00000 +----------------------------------------------------------+ | |
* | dram_ncc | | |
* 0x80A00000 +----------------------------------------------------------+ | |
* | postram_dma_coherent_dram | v v
* | postram_dma_coherent_dram | | |
* 0x80004000 +----------------------------------------------------------+ | |
* | POSTRAM STACK | v v
* 0x80000000 +----------------------------------------------------------+ <--------------
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX
* 0x24060000 +----------------------------------------------------------+ <---------
@ -163,7 +165,7 @@
* 0x146A5000 +----------------------------------------------------------+ |
* | AOP SDI | |
* 0x14699000 +----------------------------------------------------------+ |
* | STACK | v
* | PRERAM STACK | v
* 0x14680000 +----------------------------------------------------------+ <---------
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX
* 0x0B100000 +----------------------------------------------------------+ <---------
@ -186,7 +188,7 @@ SECTIONS
AOPSRAM_END(0x0B100000)
SSRAM_START(0x14680000)
STACK(0x14680000, 16K)
PRERAM_STACK(0x14680000, 16K)
REGION(aop_sdi, 0x14699000, 48K, 4K)
REGION(shared_imem, 0x146AA000, 0x1000, 4K)
REGION(ddr_information, 0x146ABFE8, 16, 8)
@ -221,7 +223,8 @@ SECTIONS
REGION(shrm, 0x24040000, 128K , 4K)
DRAM_START(0x80000000)
POSTRAM_DMA_COHERENT(0x80000000, 8K)
POSTRAM_STACK(0x80000000, 16K)
POSTRAM_DMA_COHERENT(0x80004000, 8K)
REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)