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soc/intel/common: Enable high address support for MCHBAR in ACPI

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Increased MHBR field width in ACPI northbridge.asl from 17 to 27 bits,
allowing MCHBAR to be set above 4GB (up to 42 bits).

Reference: Section 10.3 in 850519
BUG=none
TEST=boot to OS with ACPI debug enabled and check GMHB log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I885ff64598367ddadcec05926af3556024b61250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90729
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Wonkyu Kim 2025-12-29 13:35:33 -08:00 • committed by Jérémy Compostella
commit 5f86aba4b3
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/common/block/acpi/acpi/northbridge.asl
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@ -24,7 +24,7 @@ Device (MCHC)
Offset(0x48), /* MCHBAR (0:0:0:48) */
MHEN, 1, /* Enable */
, 14,
MHBR, 17, /* MCHBAR [31:15] */
MHBR, 27, /* MCHBAR [41:15] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */
PXEN, 1, /* Enable */
@ -246,6 +246,7 @@ Method (_CRS, 0, Serialized)
Method (GMHB, 0, Serialized)
{
Local0 = \_SB.PCI0.MCHC.MHBR << 15
Printf ("GMHB: %o", ToHexString(Local0))
Return (Local0)
}