soc/intel/alderlake: add chipsetinit support
Intel chipsetinit.bin is for PCH modphy initialize.
Add code to read chipsetinit.bin from CBFS and fill UPD params.
BUG=b:447290550
TEST=1. build coreboot
2. check log to confirm load chipsetinit.bin successfully.
Change-Id: I65740f52c779daeea1a27a9e078336daee29cf3b
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90687
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kao, Ben <ben.kao@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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2 changed files with 32 additions and 0 deletions
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@ -396,6 +396,19 @@ config CONSOLE_CBMEM_BUFFER_SIZE
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default 0x100000 if BUILDING_WITH_DEBUG_FSP
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default 0x40000
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config CHIPSETINIT_CBFS_FILE
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string
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depends on HAVE_CHIPSETINIT_BINARY
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default "chipsetinit.bin"
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help
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Name of the Chipset Initialization binary on the CBFS
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config HAVE_CHIPSETINIT_BINARY
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bool
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default n
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help
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Select this option if you want to load the Chipset Initialization binary
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config FSP_TYPE_IOT
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bool
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default n
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@ -664,6 +664,22 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
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s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
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}
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#if CONFIG(HAVE_CHIPSETINIT_BINARY)
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static void fill_fsps_chipsetinit_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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void *data;
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size_t size;
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data = cbfs_map(CONFIG_CHIPSETINIT_CBFS_FILE, &size);
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if (!data || size == 0)
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return;
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s_cfg->ChipsetInitBinPtr = (uint32_t)(uintptr_t)data;
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s_cfg->ChipsetInitBinLen = (uint32_t)size;
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}
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#endif
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static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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@ -1284,6 +1300,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
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fill_fsps_cpu_params,
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fill_fsps_igd_params,
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fill_fsps_tcss_params,
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#if CONFIG(HAVE_CHIPSETINIT_BINARY)
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fill_fsps_chipsetinit_params,
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#endif
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fill_fsps_chipset_lockdown_params,
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fill_fsps_xhci_params,
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fill_fsps_xdci_params,
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