soc/mediatek: Drop mtk_ddp_soc_mode_set()

We'd like to replace dsc_cfg->pic_width with edid->mode.ha in MT8196's
dsc_configure_registers() and then deprecate the 'pic_width' field. To
do that, we will first need to pass the edid struct pointer from
mtk_ddp_mode_set() all the way to that function.

Currently mtk_ddp_mode_set() is in the MediaTek common code, which calls
SoC's mtk_ddp_soc_mode_set(), but the edid isn't passed. To simplify the
edid pointer passing, drop mtk_ddp_soc_mode_set() and replace it with
SoC's mtk_ddp_mode_set(). To minimize the duplicate code of calculating
vrefresh, introduce mtk_get_vrefresh() to the display API, and reference
it from SoC's code.

BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none

Change-Id: Ifb84c6b954dde2f25c3ac491a5392b7725c13a43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90559
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>

src/soc/mediatek/common/display.c

@@ -184,12 +184,13 @@ int mtk_display_init(void)
 	name = edid.ascii_string;
 	if (name[0] == '\0')
 		name = "unknown name";
-	printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__,
-	       edid.manufacturer_name, name, edid.mode.ha, edid.mode.va,
-	       edid.mode.refresh);
 
 	edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
 
+	printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz bpp %u\n", __func__,
+	       edid.manufacturer_name, name, edid.mode.ha, edid.mode.va,
+	       edid.mode.refresh, edid.framebuffer_bits_per_pixel / 8);
+
 	mtk_ddp_mode_set(&edid, panel->disp_path, dsc_config_var);
 
 	if (panel->disp_path == DISP_PATH_EDP) {
@@ -215,28 +216,23 @@ int mtk_display_init(void)
 	return 0;
 }
 
-void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
-		      struct dsc_config *dsc_config)
+u32 mtk_get_vrefresh(const struct edid *edid)
 {
-	u32 fmt = OVL_INFMT_RGBA8888;
-	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
 	u32 width = edid->mode.ha;
 	u32 height = edid->mode.va;
 	u32 vrefresh = edid->mode.refresh;
 
-	printk(BIOS_DEBUG, "%s: display resolution: %ux%u@%u bpp %u\n", __func__, width, height,
-	       vrefresh, bpp);
+	if (vrefresh)
+		return vrefresh;
 
-	if (!vrefresh) {
-		if (!width || !height)
-			vrefresh = 60;
-		else
-			vrefresh = edid->mode.pixel_clock * 1000 /
-				   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
+	if (!width || !height)
+		vrefresh = 60;
+	else
+		vrefresh = edid->mode.pixel_clock * 1000 /
+			   ((width + edid->mode.hbl) * (height + edid->mode.vbl));
 
-		printk(BIOS_WARNING, "%s: vrefresh is not provided; using %u\n", __func__,
-		       vrefresh);
-	}
+	printk(BIOS_WARNING, "%s: vrefresh is not provided; using %u\n", __func__,
+	       vrefresh);
 
-	mtk_ddp_soc_mode_set(fmt, bpp, width, height, vrefresh, path, dsc_config);
+	return vrefresh;
 }

src/soc/mediatek/common/include/soc/display.h

@@ -4,6 +4,7 @@
 #define __SOC_MEDIATEK_COMMON_DISPLAY_H__
 
 #include <commonlib/coreboot_tables.h>
+#include <edid.h>
 #include <mipi/panel.h>
 #include <stdbool.h>
 
@@ -33,8 +34,7 @@ void mtk_display_disable_secure_mode(void);
 int mtk_display_init(void);
 
 void mtk_ddp_init(void);
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config);
+u32 mtk_get_vrefresh(const struct edid *edid);
 void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
 		      struct dsc_config *dsc_config);
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr, const struct edid *edid,

src/soc/mediatek/mt8186/ddp.c

@@ -142,10 +142,15 @@ void mtk_ddp_init(void)
 	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 }

src/soc/mediatek/mt8188/ddp.c

@@ -146,10 +146,15 @@ void mtk_ddp_init(void)
 	write32p(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0, 0);
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 }

src/soc/mediatek/mt8189/ddp.c

@@ -138,10 +138,15 @@ void mtk_ddp_init(void)
 	       __func__, read32(&smi_larb0->port_l0_ovl_rdma[0]));
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh, path);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 }

src/soc/mediatek/mt8195/ddp.c

@@ -151,11 +151,16 @@ void mtk_ddp_init(void)
 	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	main_disp_path_setup(width, height, vrefresh);
 	rdma_start();
-	ovl_layer_config(fmt, bpp, width, height);
+	ovl_layer_config(OVL_INFMT_RGBA8888, bpp, width, height);
 	ovl_bgclr_in_sel(1);
 }

src/soc/mediatek/mt8196/ddp.c

@@ -685,14 +685,19 @@ void mtk_ddp_init(void)
 	disp_clock_on();
 }
 
-void mtk_ddp_soc_mode_set(u32 fmt, u32 bpp, u32 width, u32 height, u32 vrefresh,
-			  enum disp_path_sel path, struct dsc_config *dsc_config)
+void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path,
+		      struct dsc_config *dsc_config)
 {
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = mtk_get_vrefresh(edid);
+
 	if (width > 0x1FFF || height > 0x1FFF)
 		printk(BIOS_WARNING, "%s: w/h: %d/%d exceed hw limit %u\n", __func__,
 		       width, height, 0x1FFF);
 	main_disp_path_setup(width, height, vrefresh, path, dsc_config);
-	ovlsys_layer_config(fmt, bpp, width, height, path);
+	ovlsys_layer_config(OVL_INFMT_RGBA8888, bpp, width, height, path);
 }
 
 void mtk_ddp_ovlsys_start(uintptr_t fb_addr, const struct edid *edid,