coreboot already has a way to configure wakeup from wireless through
the `wifi/generic` driver, so remove these to avoid conflicts.
Change-Id: I744ef37690b7a2478ec29a43b987b43592df2235
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86506
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for VMD (Volume Management Device) in the
Panther Lake SoC. VMD is a feature that allows the management of NVMe
storage devices by abstracting the PCIe root complex. It provides a way
to manage multiple NVMe drives more efficiently.
Changes include:
- Adding VMD to the `min_pci_sleep_states` array in `acpi.c`.
- Updating `chipset.cb` to include the VMD device.
- Disabling the VMD device by default.
- Introducing a new function `fill_fsps_vmd_params`.
- Defining the VMD device and function numbers in `pci_devs.h`.
BUG=b:391083063
TEST=Able to build and boot google/fatcat. Observed that VmdEnable UPD
is disabled in debug FSP logs.
Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
In the Panther Lake architecture, each GPIO community functions as a
separate pin control entity. Therefore, when specifying a GPIO
identifier, one should use the community-specific offset, not the number
from the first pad within the GPIO series. This is achieved by selecting
the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within
the Panther Lake SOC Kconfig file.
The numbers within the _CRS GpioInt and GpIo objects in the SSDT should
be offsets within the community. The GPIO identifier employed should
correspond to the offset from the respective community.
Let's take an example. In the fatcat board overridetree.cb,
ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad
starts at 74. It is inside community 1, which starts at 48. The correct
GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal.
Here are two notable changes in the fatcat board SSDT introduced by this
commit.
- ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)
"\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, ,
)
{ // Pin list
- 0x0033
+ 0x002D
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
- ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)
"\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, ,
)
{ // Pin list
- 0x0050
+ 0x003B
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
This change is verified via S0ix in Google Fatcat board with
touchscreen/touchpad attached as the wake source.
BUG=none
TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and
ensure that the GPIO number used matches the community offset.
Configure touchscreen/touchpad in THC-i2c mode on factcat board and
enter S0ix and check that it can be waked by touchscreen/touchpad.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit enables Thunderbolt authentication for Panther Lake by
assigning `ioe_tcss_valid_tbt_auth` to the valid_tbt_auth field in
`soc_tcss_ops`.
For the SoC's integrated PD solution, AUX BIAS PAD programming is not
required and has been removed.
TEST=Verified all USB-C ports are functional.
With this patch, \_SB.PCI0.TDM0._DSD exists in the SSDT, containing:
```
Scope (\_SB.PCI0.TDM0)
{
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("c44d002f-69f9-4e7d-a904-a7baabdf43f7"),
Package (0x01)
{
Package (0x02)
{
"IMR_VALID",
One
}
},
ToUUID ("6c501103-c189-4296-ba72-9bf5a26ebe5d"),
Package (0x01)
{
Package (0x02)
{
"WAKE_SUPPORTED",
One
}
}
}
```
Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch prevents exposing the CPU JTAG GPIO pads. These are
internal GPIO pins used for debugging the SoC and should not be
configurable from the kernel pinctrl driver.
TEST=Able to build and boot google/fatat. Decompile ACPI table
using iasl and ensure CPUJTAG entry not present.
Change-Id: I4d920acb95275fbf72b83b822eddc41829511626
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ife30f73495d44c98717e147602de10f5a6a89358
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ic226fd93b431467c7fa3a53140102ff4fd327f40
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86271
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86270
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables the `HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR`
Kconfig option for Alder Lake SoC platform that has support for
CHROMEOS_ENABLE_ESOL.
This allows the eSOL feature (depending upon CHROMEOS_ENABLE_ESOL)
to display a low-battery indicator.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: I8b49a487ca80a2aeeb8b4d8e4c2259217e854444
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86316
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit implements early handling of critical low battery
conditions in the romstage for Alder Lake platforms.
A message is displayed to the user via
ux_inform_user_of_poweroff_operation. A short delay is introduced to
allow the user to see the message. A low battery event is logged.
The system is shut down via the Chrome EC.
This early handling prevents the system from proceeding with
boot (while performing firmware update) if the battery is critically
low and ensures a clean shutdown. This is particularly important for
ChromeOS devices.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86227
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a `do_low_battery_poweroff()` function to handle
platform power off due to critically low battery levels.
This provides a standardized way to handle low battery shutdowns across
platforms.
Additionally, the delay to the `do_low_battery_poweroff()` function,
allowing time for the low battery indicator to be displayed before
powering off. The delay is configurable through the
`PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC` Kconfig option.
Finally, a low battery indicator event is logged using `elog`
before the delay.
This functionality (elog and delay) is enabled when the
`PLATFORM_HAS_LOW_BATTERY_INDICATOR` Kconfig option is selected.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86361
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for early power off on Intel platforms
along with existing PMC based implementation to support power off
at later stage (like ramstage).
A new function, `platform_do_early_poweroff`, is added to the
pmclib to handle platform-specific early power off procedures.
This function is called before memory initialization (in romstage or
earlier).
Note: While Intel chipsets do not support power off before silicon
initialization, this change leverages Chrome EC APIs to enable power off
in romstage for low-battery boot on ChromeOS devices. Power off failures
in ramstage prior to FSP-S are outside the scope of this change.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit adds a function ux_inform_user_of_poweroff_operation
to display a message on the screen when the system is powering off due
to critically low battery. The message is centered on the screen and
displays a localized string "Battery critically low. Shutting down.".
If no localized string is found, a default English message is displayed.
This implementation relies on CHROMEOS_ENABLE_ESOL Kconfig which is used
to render text message for early sign-of-life.
BUG=b:339673254
TEST=Able to capture the eventlog for low battery boot event.
Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86224
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces `ux_inform_user_of_operation` to reduce code
duplication when displaying UX messages.
`ux_inform_user_of_update_operation` now calls this helper, passing
the message ID. This allows easier addition of other UX messages.
BUG=b:339673254
TEST=Built and booted google/brox. Verified display eSOL.
Change-Id: Ib31f7633e7b3f84122419e4ce39e2b5044cb9a96
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86278
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch refactors the `ux_locales_get_text` API to handle fallback
text (English) internally, rather than relying on the caller. It
introduces message IDs for lookups, enabling the API to locate both
the UX locale name and fallback text based on the ID.
With this patch, `ux_locales_get_text` API locates UX locales message
based on message ID.
`ux_locales_get_text` retrieves fallback text message depending
upon the message ID if UX locales is not available.
This centralizes fallback handling and simplifies adding future
messages without per-SoC duplication.
BUG=b:339673254
TEST=Built and booted google/brox. Verified eSOL display.
Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Move the VBIOS checksum code into the soc/amd folder, as it's
specific to AMD's FSP. The code now fixes the VBIOS in place
instead only fixing it for the VFCT table.
TEST: VBIOS has correct checksum after loading in BS_DEV_RESOURCES.
VBIOS checksum is invalid entering graphics_dev_init().
VBIOS checksum is correct leaving graphics_dev_init().
Change-Id: I63aaaefaf01ea456e2ed39cd0891e552a7fb5135
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86384
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On glinda the IGD is no longer VGA compatible. It doesn't
advertise itself as a VGA compatible devices and doesn't decode
the legacy VGA ranges 0x3C0-0x3CF, 0x3D4.
Introduce a new Kconfig and select it where necessary to keep
existing behaviour on older SoC while fixing FSP GOP init on
glinda. The VBIOS will get loaded into the D-segment instead
the C-segment, which is typically used by VGA.
TEST: FSP GOP on amd/birman+ is able to find the VBIOS.
amdgpu driver still doesn't work as the VFCT table isn't
generated on amd/glinda.
Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86300
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement vbt_get() on AMD and return the VBIOS location. This allows
to drop the hardcoded addresses used in various places and return an
address in DRAM that is reserved for FSP use.
TEST: amd/birman+ still gets passed the correct VBIOS address.
Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86299
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
To fix the SPMI-P glitch, set the mt6316 deglitch time from 2ns to 4ns.
Additionally, a hardware solution of SPMI damping to 0 ohm is needed.
BRANCH=rauru
TEST=Build passed and booted successfully. 10 platforms have passed CPU
stress tests over multiple iterations.
BUG=b:386438329
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Configure PMIC register 0x50c bit0 which decides whether to use external
xtal. This bit of mt6685 should be set to 1, to disable external xtal.
BRANCH=rauru
BUG=b:395485005
TEST=emerge-rauru coreboot chromeos-bootimage, remove battery and
charger, then insert battery and charge, RTC boots normally.
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Change-Id: Iea44f13af030f24c02993dd43a35a9d8b4f72179
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86353
Reviewed-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The tvdpll3 cannot be disabled during suspend because of the enable
operation, so we remove the enable operation. Hardware can now
automatically enable and disable tvdpll3 based on the clock demand of
its downstream.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra
kernel/vcp patch, mminfra can be turned off to reduce power consumption.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86343
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
As MT8196 won't be able to boot up without mtk_fsp_romstage.elf and
mtk_fsp_ramstage.elf, ensure their presence in build time.
Change-Id: I668319ae1f63818e324002e7ae4d888479edb9cf
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Correct MMinfra vote register to fix MMinfra power off failure during
suspend.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch,
mminfra can be turned off to reduce power consumption by 50mW.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86342
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to a maximum value of 16mA. Additionally, a hardware solution of
external pull-down is also required.
BRANCH=rauru
TEST=Build passed and booted successfully. The platform remained idle
for approximately 20 hours without hang.
BUG=b:383634290
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The code flow isn't that obvious in the beginning. You pass an address
of the VBIOS to FSP, but don't load any VBIOS until BS_DEV_RESOURCES
phase.
Add comments to document what is done and when. This will help to
improve the code in the next step.
Change-Id: I643bc9088306d99cc0fbb79648809e16b068fb33
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch disables eSOL Kconfig until the feature is ready in PTL
FSP-uGOP binary.
TEST=Able to build and boot google/fatcat to OS.
Change-Id: I99dd516816995b6cdfdcec618c06c7dbe061718a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86314
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TCSS_XHCI controller has a single USB2 port followed by 4 USB3
ports; the XHCI controller has 12 USB2 ports followed by 2 USB3
ports. The topology was queried from the root hub on each controller
and returned via the descriptor.
Add the 2 missing USB2 ports to the XHCI controller and the one to
the TSS_XHCI controller.
TEST=build/boot Win11, Linux 6.x on starlabs/starbook_mtl.
Change-Id: I5dc97f150ff064d55e7969f10c1cea8ba72d6bfb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Measure mtk_fsp_load_and_run() execution time. This info helps AP boot
time analysis. The logs show as below.
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase 0x30 in 0 msecs
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase 0x50 in 41 msecs
BUG=none
BRANCH=rauru
TEST=cbmem -1|grep "mtk_fsp_load_and_run"
Change-Id: I61706952bef4590c5bfd09707a08a4f1a25fbda2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Linux complains in dmesg as a firmware bug that BSP is not the first
entry.
NetBSD hangs and OpenBSD panics early on boot.
With this patch I was able to boot NetBSD and OpenBSD on darp10-b when
loaded in GRUB.
Note: vanilla bootloaders for NetBSD and OpenBSD still result in an
apparent hang for an unknown reason.
Change-Id: I520a2e080c9f07a5866729ae2283990d20c0d691
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This prevents Windows from displaying the IOM device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify IOM device
not shown as unknown device in Device Manager.
Change-Id: Ib31018173126737b36a6e0d822eba2ebc9c42306
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86257
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This prevents Windows from displaying the PMC device in Device Manager
as an unknown device with no driver available, and brings Alderlake
and Tigerlake in line with Meteorlake and Pantherlake.
TEST=build/boot Win11 on starlabs/starlite_adl, verify PMC device
not shown as unknown device in Device Manager.
Change-Id: I4bd62d113455fab7fcb272d85f70e6a185e53b74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Previously only the '06-37-03' and '06-37-09' microcode files were provided
but '06-37-08' was missing.
Linux on my '06-37-08' SOC was segfaulting in various unpredictable ways without
this patch.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MSEC_TO_USEC(cse_perf_data.timestamp[i]) does overflow.
Here is an example, if cse_perf_data.timestamp[i] value is
4304903 milliseconds. When multiplied by 1000 to convert to
microseconds, the value becomes 0x979B58 instead of 0x100979B58.
TEST=Boot to OS
Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86215
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Remove the memcpy_s function as it is not used.
Additionally, the function did not return the expected values:
0: If the memory copy is successful.
EINVAL: If dest or src is a null pointer, or if count is greater
than RSIZE_MAX.
ERANGE: If count is greater than destsz.
Change-Id: I0d32c838e94ae760907efe55ed00bab3faaaa8c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86233
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Have two comments, then two blocks of code makes it hard to read.
Seperate them.
Change-Id: I32d6b7c389f64305e8357f52b063628cd99816d6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86196
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently after UFS is disabled, if the device is coming out of S5 sleep
state then a warm reset is triggered such that PMC samples the UFS
function disable bit and disables the UFS controller accordingly.
Sometimes during the boot flow, an additional kind of reset gets
triggered - Power cycle Reset through CMoff. Hence initiate a warm reset
when the host comes out of S5 sleep state or Power cycle Reset through
CMoff.
BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS. Ensure that when the device
switches from normal mode to developer mode an extra warm reset is
triggered such that the UFS controller is disabled.
Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86170
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Introduce an API to read the Converged Security and Management Engine
(CSME) host firmware status register to obtain the current Power
Management event and compare it with a specified input event.
BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS.
Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86169
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
The message printed when duplicate GPE DW register values are
detected was previously logged at the INFO level. This commit
changes the log level to WARNING, as duplicate DW values indicate
a potential misconfiguration and warrant closer attention. While
the system falls back to the default GPE route (as per MISCCFG
register), this situation should be investigated to ensure correct
platform configuration.
This change ensures that developers are more clearly notified of
potential GPE routing issues.
TEST=Built and booted on a platform using PMC GPE routing. Verified
that the message is printed at the WARNING level when duplicate DW
values are present.
Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `pmc_gpe_init` function's check for duplicate GPE DW register values
was incomplete. It only checked for duplicates between DW0 and DW1, and
DW1 and DW2, but failed to check if DW0 and DW2 were the same.
This could lead to incorrect GPE routing if DW0 and DW2 happened to have
the same value, even if DW1 was different.
This commit corrects the check to ensure that all three DW registers
(DW0, DW1, and DW2) are compared against each other. If any two
registers have the same value, a message is printed indicating that
the default GPE route will be used.
Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `pmc_gpe0_different_values` function previously asserted if any
two of the GPE0 DW registers (DW0, DW1, DW2) had the same value, as
introduced in commit 640a41f3ee ("soc/intel: Assert if
`pmc_/gpe0_dwX` values are not unique"). This prevented platforms from
configuring GPE routing via PMC as per default register (MISCCFG) value.
This commit modifies the check to allow all DW registers to be zero.
This enables platforms that rely on MISCCFG register for
PMC-controlled GPE routing to boot without triggering the assertion.
The change was verified by testing the following scenarios:
- All DWs zero: The system boots using the default GPE route.
No assertion occurs.
- Duplicate DWs (e.g., DW0=1, DW1=2, DW2=2): The existing assertion
is triggered as expected.
- Unique DWs (e.g., DW0=1, DW1=2, DW2=3): No errors occur.
TEST=Built and booted normally. No assertion failure observed.
Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86164
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
