soc/intel/cmn/pmc: Add support for early power off
This commit adds support for early power off on Intel platforms along with existing PMC based implementation to support power off at later stage (like ramstage). A new function, `platform_do_early_poweroff`, is added to the pmclib to handle platform-specific early power off procedures. This function is called before memory initialization (in romstage or earlier). Note: While Intel chipsets do not support power off before silicon initialization, this change leverages Chrome EC APIs to enable power off in romstage for low-battery boot on ChromeOS devices. Power off failures in ramstage prior to FSP-S are outside the scope of this change. BUG=b:339673254 TEST=Able to build and boot google/brox. Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
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1 changed files with 16 additions and 1 deletions
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@ -15,6 +15,7 @@
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#include <intelblocks/gpio.h>
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#include <intelblocks/tco.h>
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#include <option.h>
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#include <reset.h>
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#include <security/vboot/vboot_common.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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@ -615,7 +616,8 @@ void vboot_platform_prepare_reboot(void)
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pmc_write_pm1_control(pm1_cnt);
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}
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void poweroff(void)
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/* Helper function to perform poweroff operation using PMC chipset register. */
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static void pmc_control_poweroff(void)
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{
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pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
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@ -628,6 +630,19 @@ void poweroff(void)
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halt();
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}
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void poweroff(void)
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{
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if (!ENV_ROMSTAGE_OR_BEFORE) {
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pmc_control_poweroff();
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} else if (CONFIG(HAVE_EARLY_POWEROFF_SUPPORT)) {
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platform_do_early_poweroff();
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} else {
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printk(BIOS_EMERG, "This platform cannot be powered off until the silicon"
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" initialization is complete, hanging!\n");
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halt();
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}
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}
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void pmc_gpe_init(void)
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{
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uint32_t gpio_cfg = 0;
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