soc/amd/glinda: Fix pci int defs

commit 540d605f48 ("soc/amd/glinda: Update pci int defs") forgot to
update the offset after adding GEventSmi and GEventSci.

source:
PPR #57254 Rev 1.59 Table 137

Change-Id: I702f16e681d57c5e44f91c805a9aeb71eb160bd3
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/soc/amd/glinda/acpi/pci_int_defs.asl

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Glinda */
-
 /* PCI IRQ mapping registers, C00h-C01h. */
 OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
 	Field(PRQM, ByteAcc, NoLock, Preserve) {
@@ -51,7 +49,7 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
 	IORG, 0x00000008,	/* Index 0x86: INTG */
 	IORH, 0x00000008,	/* Index 0x87: INTH */
 
-	Offset (0xE2),
+	Offset (0xE0),
 	IGSC, 0x00000008,	/* Index 0xE0: GEventSci */
 	IGSM, 0x00000008,	/* Index 0xE1: GEventSmi */
 	IGPI, 0x00000008,	/* Index 0xE2: GPIO */