tree: Use boolean for PchHdaDspEnable

Change-Id: I47852c9b023cc4839000019b8a932b6e471fa839
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>

src/mainboard/google/dedede/variants/baseboard/devicetree.cb

@@ -129,7 +129,7 @@ chip soc/intel/jasperlake
 	register "PcieClkSrcClkReq[5]" = "5"
 
 	# Audio related configurations
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHdaEnable" = "1"
 	register "PchHdaAudioLinkSspEnable[0]" = "1"
 	register "PchHdaAudioLinkSspEnable[1]" = "1"

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -177,7 +177,7 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	#Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override)
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkSsp0" = "1"
 	register "PchHdaAudioLinkSsp1" = "1"
 	register "PchHdaAudioLinkDmic0" = "1"

src/mainboard/google/puff/variants/baseboard/devicetree.cb

@@ -177,7 +177,7 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[3]" = "3"
 
 	#Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override)
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkSsp0" = "1"
 	register "PchHdaAudioLinkSsp1" = "1"
 	register "PchHdaAudioLinkDmic0" = "1"

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -506,7 +506,7 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref hda on
-			register "PchHdaDspEnable" = "1"
+			register "PchHdaDspEnable" = "true"
 
 			chip drivers/sof
 				register "spkr_tplg" = "max98373"

src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb

@@ -22,7 +22,7 @@ chip soc/intel/cannonlake
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
 
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
 	register "PcieClkSrcUsage[0]" = "1"

src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb

@@ -39,7 +39,7 @@ chip soc/intel/cannonlake
 	register "SataPortsEnable[6]" = "1"
 	register "SataPortsEnable[7]" = "1"
 
-	register "PchHdaDspEnable" = "0"
+	register "PchHdaDspEnable" = "false"
 	register "PchHdaAudioLinkHda" = "1"
 
 	register "PcieRpEnable[0]" = "true"

src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb

@@ -37,7 +37,7 @@ chip soc/intel/cannonlake
 	register "SataPortsEnable[6]" = "1"
 	register "SataPortsEnable[7]" = "1"
 
-	register "PchHdaDspEnable" = "0"
+	register "PchHdaDspEnable" = "false"
 	register "PchHdaAudioLinkHda" = "1"
 
 	register "PcieRpEnable[0]" = "true"

src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/cannonlake
 
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
 	register "PcieRpEnable[0]" = "true"

src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb

@@ -38,7 +38,7 @@ chip soc/intel/cannonlake
 	register "SataPortsEnable[6]" = "1"
 	register "SataPortsEnable[7]" = "1"
 
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
 	register "PcieRpEnable[0]" = "true"

src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb

@@ -23,7 +23,7 @@ chip soc/intel/cannonlake
 	register "SataPortsEnable[6]" = "1"
 	register "SataPortsEnable[7]" = "1"
 
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHda" = "1"
 
 	register "PcieRpEnable[0]" = "true"

src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb

@@ -56,7 +56,7 @@ chip soc/intel/jasperlake
 	# Skip the CPU replacement check
 	register "SkipCpuReplacementCheck" = "1"
 
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHdaEnable" = "0"
 	register "PchHdaAudioLinkSspEnable[0]" = "1"
 	register "PchHdaAudioLinkSspEnable[1]" = "1"

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -322,7 +322,7 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref hda on
-			register "PchHdaDspEnable" = "1"
+			register "PchHdaDspEnable" = "true"
 			register "PchHdaAudioLinkDmicEnable" = "{
 				[0] = 1,
 				[1] = 1,

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -325,7 +325,7 @@ chip soc/intel/tigerlake
 			end
 		end
 		device ref hda on
-			register "PchHdaDspEnable" = "1"
+			register "PchHdaDspEnable" = "true"
 			register "PchHdaAudioLinkDmicEnable" = "{
 				[0] = 1,
 				[1] = 1,

src/mainboard/prodrive/hermes/devicetree.cb

@@ -23,7 +23,7 @@ chip soc/intel/cannonlake
 	register "SataPortsHotPlug[6]" = "1"
 	register "SataPortsHotPlug[7]" = "1"
 
-	register "PchHdaDspEnable" = "0"
+	register "PchHdaDspEnable" = "false"
 	register "PchHdaAudioLinkHda" = "1"
 
 	register "PcieClkSrcUsage[0]" = "20"		# PCIe Slot1

src/mainboard/purism/librem_jsl/devicetree.cb

@@ -39,7 +39,7 @@ chip soc/intel/jasperlake
 	register "SerialIoUartMode[2]" = "PchSerialIoSkipInit"
 
 	# Audio related configurations
-	register "PchHdaDspEnable" = "1"
+	register "PchHdaDspEnable" = "true"
 	register "PchHdaAudioLinkHdaEnable" = "1"
 
 	device domain 0 on

src/mainboard/siemens/chili/variants/base/devicetree.cb

@@ -4,7 +4,7 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "RMT" = "0"
 
-	register "PchHdaDspEnable" = "0"
+	register "PchHdaDspEnable" = "false"
         register "PchHdaAudioLinkHda" = "1"
 
 	device domain 0 on

src/mainboard/siemens/chili/variants/chili/devicetree.cb

@@ -4,7 +4,7 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "RMT" = "0"
 
-	register "PchHdaDspEnable" = "0"
+	register "PchHdaDspEnable" = "false"
         register "PchHdaAudioLinkHda" = "1"
 
 	device domain 0 on

src/soc/intel/elkhartlake/chip.h

@@ -203,7 +203,7 @@ struct soc_intel_elkhartlake_config {
 	uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS];
 
 	/* Audio related */
-	uint8_t PchHdaDspEnable;
+	bool PchHdaDspEnable;
 	uint8_t PchHdaAudioLinkHdaEnable;
 	uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS];
 	uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];

src/soc/intel/tigerlake/chip.h

@@ -249,7 +249,7 @@ struct soc_intel_tigerlake_config {
 	uint16_t SataPortsDitoVal[8];
 
 	/* Audio related */
-	uint8_t PchHdaDspEnable;
+	bool PchHdaDspEnable;
 	uint8_t PchHdaAudioLinkHdaEnable;
 	uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
 	uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];