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soc/intel/common/pmc: Fix duplicate GPE DW register check

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The `pmc_gpe_init` function's check for duplicate GPE DW register values
was incomplete. It only checked for duplicates between DW0 and DW1, and
DW1 and DW2, but failed to check if DW0 and DW2 were the same.

This could lead to incorrect GPE routing if DW0 and DW2 happened to have
the same value, even if DW1 was different.

This commit corrects the check to ensure that all three DW registers
(DW0, DW1, and DW2) are compared against each other. If any two
registers have the same value, a message is printed indicating that
the default GPE route will be used.

Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Subrata Banik 2025-01-28 12:49:20 +05:30 • committed by Sean Rhodes
commit 60b55cc70b
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/common/block/pmc/pmclib.c
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@ -656,7 +656,7 @@ void pmc_gpe_init(void)
* Route the GPIOs to the GPE0 block. Determine that all values
* are different, and if they aren't use the reset values.
*/
if (dw0 == dw1 || dw1 == dw2) {
if (dw0 == dw1 || dw1 == dw2 || dw0 == dw2) {
printk(BIOS_INFO, "PMC: Using default GPE route.\n");
gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG);