soc/mediatek/mt8196: Remove tvdpll3 disable/enable

The tvdpll3 cannot be disabled during suspend because of the enable
operation, so we remove the enable operation. Hardware can now
automatically enable and disable tvdpll3 based on the clock demand of
its downstream.

BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra
kernel/vcp patch, mminfra can be turned off to reduce power consumption.

Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86343
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8196/pll.c

@@ -1572,11 +1572,7 @@ void mt_pll_set_tvd_pll1_freq(u32 freq)
 {
 	const struct pll *pll = &plls[CLK_APMIXED2_TVDPLL3];
 
-	clrbits32(pll->reg, MT8196_PLL_EN);
 	pll_set_rate(pll, freq);
-	setbits32(pll->reg, MT8196_PLL_EN);
-
-	udelay(PLL_EN_DELAY);
 }
 
 void mt_pll_edp_mux_set_sel(u32 sel)