soc/amd/common/block/graphics: Use vbt_get()

Implement vbt_get() on AMD and return the VBIOS location. This allows
to drop the hardcoded addresses used in various places and return an
address in DRAM that is reserved for FSP use.

TEST: amd/birman+ still gets passed the correct VBIOS address.

Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86299
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>

src/drivers/intel/fsp2_0/silicon_init.c

@@ -14,7 +14,12 @@
 #include <mrc_cache.h>
 #include <program_loading.h>
 #include <soc/intel/common/reset.h>
+#if CONFIG(SOC_AMD_COMMON)
+#include <amdblocks/vbt.h>
+#endif
+#if CONFIG(SOC_INTEL_COMMON)
 #include <soc/intel/common/vbt.h>
+#endif
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>

src/soc/amd/cezanne/fsp_s_params.c

@@ -2,6 +2,7 @@
 
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
@@ -13,7 +14,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)

src/soc/amd/common/block/graphics/graphics.c

@@ -4,6 +4,7 @@
 #include <acpi/acpigen.h>
 #include <amdblocks/graphics.h>
 #include <amdblocks/vbios_cache.h>
+#include <amdblocks/vbt.h>
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
 #include <bootstate.h>
@@ -12,7 +13,6 @@
 #include <device/pci.h>
 #include <fmap.h>
 #include <security/vboot/vbios_cache_hash_tpm.h>
-#include <soc/intel/common/vbt.h>
 #include <timestamp.h>
 
 static bool vbios_loaded_from_cache = false;
@@ -146,17 +146,11 @@ static const char *graphics_acpi_name(const struct device *dev)
 	return "IGFX";
 }
 
-/*
- * On AMD platforms the VBT is called ATOMBIOS and is always part of the
- * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are
- * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP
- * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but
- * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM
- * notify is called. FSP expects a pointer to the PCI option rom instead
- * a pointer to the ATOMBIOS table directly.
- */
 void *vbt_get(void)
 {
+	if (CONFIG(RUN_FSP_GOP))
+		return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;
+
 	return NULL;
 }
 
@@ -259,12 +253,12 @@ static void write_vbios_cache_to_fmap(void *unused)
 	}
 
 	/* copy from PCI_VGA_RAM_IMAGE_START to rdev */
-	if (rdev_writeat(&rw_vbios_cache, (void *)PCI_VGA_RAM_IMAGE_START, 0,
+	if (rdev_writeat(&rw_vbios_cache, vbt_get(), 0,
 						VBIOS_CACHE_FMAP_SIZE) != VBIOS_CACHE_FMAP_SIZE)
 		printk(BIOS_ERR, "Failed to save vbios data to flash; rdev_writeat() failed.\n");
 
-	/* copy modified vbios data from PCI_VGA_RAM_IMAGE_START to buffer before hashing */
-	memcpy(vbios_data, (void *)PCI_VGA_RAM_IMAGE_START, VBIOS_CACHE_FMAP_SIZE);
+	/* copy modified vbios data to buffer before hashing */
+	memcpy(vbios_data, vbt_get(), VBIOS_CACHE_FMAP_SIZE);
 
 	/* save data hash to TPM NVRAM for validation on subsequent boots */
 	vbios_cache_update_hash(vbios_data, VBIOS_CACHE_FMAP_SIZE);
@@ -279,8 +273,8 @@ static void write_vbios_cache_to_fmap(void *unused)
  */
 void vbios_load_from_cache(void)
 {
-	/* copy cached vbios data from buffer to PCI_VGA_RAM_IMAGE_START */
-	memcpy((void *)PCI_VGA_RAM_IMAGE_START, vbios_data, VBIOS_CACHE_FMAP_SIZE);
+	/* copy cached vbios data from buffer to address used by FSP */
+	memcpy(vbt_get(), vbios_data, VBIOS_CACHE_FMAP_SIZE);
 
 	/* mark cache as used so we know not to write it later */
 	vbios_loaded_from_cache = true;

src/soc/amd/common/block/include/amdblocks/vbt.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _AMD_BLOCK_VBT_H_
+#define _AMD_BLOCK_VBT_H_
+
+/*
+ * On AMD platforms the VBT is called ATOMBIOS and is always part of the
+ * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are
+ * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP
+ * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but
+ * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM
+ * notify is called. FSP expects a pointer to the PCI Option Rom instead of
+ * a pointer to the ATOMBIOS table directly.
+ *
+ * Returns a pointer to the VGA Option ROM in DRAM after checking
+ * prerequisites for Pre OS Graphics initialization. When returning
+ * non NULL the Option ROM might not be loaded at this address yet,
+ * but is guaranteed to be present at end of BS_DEV_RESOURCES phase.
+ */
+void *vbt_get(void);
+
+#endif

src/soc/amd/glinda/fsp_s_params.c

@@ -4,6 +4,7 @@
 
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
@@ -15,7 +16,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)

src/soc/amd/mendocino/fsp_s_params.c

@@ -5,6 +5,7 @@
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
 #include <amdblocks/vbios_cache.h>
+#include <amdblocks/vbt.h>
 #include <bootmode.h>
 #include <bootsplash.h>
 #include <console/console.h>
@@ -26,7 +27,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
 	printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__);
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)

src/soc/amd/phoenix/fsp_s_params.c

@@ -4,6 +4,7 @@
 
 #include <acpi/acpi.h>
 #include <amdblocks/apob_cache.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
@@ -15,7 +16,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)

src/soc/amd/picasso/fsp_s_params.c

@@ -2,6 +2,7 @@
 
 #include <assert.h>
 #include <amdblocks/ioapic.h>
+#include <amdblocks/vbt.h>
 #include <device/pci.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -190,7 +191,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
 	 * part of FSP GOP init. We can delay loading of the VBIOS until
 	 * before FSP notify AFTER_PCI_ENUM.
 	 */
-	scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+	scfg->vbios_buffer_addr = (uintptr_t)vbt_get();
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)