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soc/intel/alderlake/romstage: Update UFS disable sequence

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Currently after UFS is disabled, if the device is coming out of S5 sleep
state then a warm reset is triggered such that PMC samples the UFS
function disable bit and disables the UFS controller accordingly.
Sometimes during the boot flow, an additional kind of reset gets
triggered - Power cycle Reset through CMoff. Hence initiate a warm reset
when the host comes out of S5 sleep state or Power cycle Reset through
CMoff.

BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS. Ensure that when the device
switches from normal mode to developer mode an extra warm reset is
triggered such that the UFS controller is disabled.

Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86170
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2025-01-27 14:47:12 -07:00 • committed by Karthik Ramasubramanian
commit 215cf2d9ab
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/alderlake/romstage/romstage.c
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@ -197,7 +197,8 @@ void mainboard_romstage_entry(void)
/* Program to Disable UFS Controllers */
if (!is_devfn_enabled(PCH_DEVFN_UFS) &&
(CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
if ((ps->prev_sleep_state == ACPI_S5 || cse_check_host_cold_reset()) &&
!mainboard_expects_another_reset()) {
printk(BIOS_INFO, "Disabling UFS controllers\n");
disable_ufs();
printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");