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tree: Use true false for PcieRpLtrEnable[]

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PcieRpLtrEnable[] is a boolean, so use true false.

Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2025-01-28 16:48:58 +01:00
commit 594dba56ec
76 changed files with 243 additions and 247 deletions
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6
src/mainboard/51nb/x210/devicetree.cb
View file

@ -94,7 +94,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[2]" = "0"
register "PcieRpClkSrcNumber[2]" = "0"
register "PcieRpAdvancedErrorReporting[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
end
device ref pcie_rp4 on
# Wireless controller
@ -103,7 +103,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[3]" = "1"
register "PcieRpClkSrcNumber[3]" = "1"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[3]" = "true"
end
device ref pcie_rp9 on
# NVMe controller
@ -112,7 +112,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[8]" = "4"
register "PcieRpClkSrcNumber[8]" = "4"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"

8
src/mainboard/acer/aspire_vn7_572g/devicetree.cb
View file

@ -253,7 +253,7 @@ chip soc/intel/skylake
# dGPU; x4
register "PcieRpEnable[0]" = "true"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "0"
register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
@ -262,7 +262,7 @@ chip soc/intel/skylake
# NGFF; x2
register "PcieRpEnable[6]" = "true"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "3"
register "PcieRpMaxPayload[6]" = "RpMaxPayload_256"
@ -271,7 +271,7 @@ chip soc/intel/skylake
# LAN
register "PcieRpEnable[8]" = "true"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "1"
register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
@ -280,7 +280,7 @@ chip soc/intel/skylake
# WLAN
register "PcieRpEnable[9]" = "true"
register "PcieRpAdvancedErrorReporting[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "true"
register "PcieRpClkReqSupport[9]" = "1"
register "PcieRpClkReqNumber[9]" = "2"
register "PcieRpMaxPayload[9]" = "RpMaxPayload_256"

6
src/mainboard/asrock/h110m/devicetree.cb
View file

@ -117,7 +117,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpClkSrcNumber[4]" = "2"
register "PcieRpHotPlug[4]" = "1"
end
@ -127,7 +127,7 @@ chip soc/intel/skylake
# Disable CLKREQ#, since onboard LAN is always present
register "PcieRpClkReqSupport[5]" = "0"
register "PcieRpAdvancedErrorReporting[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieRpClkSrcNumber[5]" = "1"
end
device ref pcie_rp7 on
@ -135,7 +135,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "3"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieRpClkSrcNumber[6]" = "3"
register "PcieRpHotPlug[6]" = "1"
end

8
src/mainboard/asrock/imb-1222/devicetree.cb
View file

@ -210,7 +210,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4)
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "true"
register "PcieRpSlotImplemented[16]" = "1"
register "PcieClkSrcUsage[7]" = "16"
register "PcieClkSrcClkReq[7]" = "7"
@ -218,14 +218,14 @@ chip soc/intel/cannonlake
end
device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieClkSrcUsage[3]" = "4"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1)
register "PcieRpEnable[5]" = "true"
register "PcieRpSlotImplemented[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieClkSrcUsage[5]" = "5"
register "PcieClkSrcClkReq[5]" = "5"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X"
@ -233,7 +233,7 @@ chip soc/intel/cannonlake
device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1)
register "PcieRpEnable[6]" = "true"
register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieClkSrcUsage[6]" = "6"
register "PcieClkSrcClkReq[6]" = "6"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/B 3042/3052 (M2_KEYB1)" "SlotDataBusWidth1X"

8
src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
View file

@ -113,7 +113,7 @@ chip soc/intel/cannonlake
device ref pcie_rp6 on
device pci 00.0 on end # x1 Card reader
register "PcieRpEnable[5]" = "true"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieClkSrcUsage[3]" = "5"
register "PcieClkSrcClkReq[3]" = "3"
end
@ -122,7 +122,7 @@ chip soc/intel/cannonlake
device pci 00.0 on end
end
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieRpSlotImplemented[7]" = "1"
@ -130,7 +130,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[8]" = "1"
@ -138,7 +138,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp13 on
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[12]" = "1"

8
src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
View file

@ -71,7 +71,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "4"
register "PcieRpClkSrcNumber[0]" = "4"
register "PcieRpHotPlug[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
end
device ref pcie_rp5 on
@ -80,7 +80,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
end
device ref pcie_rp6 on
device pci 00.0 on end # x1 WLAN
@ -88,7 +88,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "2"
register "PcieRpClkSrcNumber[5]" = "2"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
device ref pcie_rp9 on
@ -97,7 +97,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "5"
register "PcieRpClkSrcNumber[8]" = "5"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
end
device ref lpc_espi on

2
src/mainboard/dell/optiplex_3050/devicetree.cb
View file

@ -43,7 +43,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[20]" = "1"
register "PcieRpClkReqNumber[20]" = "3"
register "PcieRpAdvancedErrorReporting[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieRpClkSrcNumber[20]" = "3"
register "PcieRpHotPlug[20]" = "1"
end

6
src/mainboard/facebook/monolith/devicetree.cb
View file

@ -160,7 +160,7 @@ chip soc/intel/skylake
register "PcieRpEnable[2]" = "true"
register "PcieRpClkReqSupport[2]" = "0"
register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
register "PcieRpAdvancedErrorReporting[2]" = "1"
register "pcie_rp_aspm[2]" = "AspmDisabled"
end
@ -170,7 +170,7 @@ chip soc/intel/skylake
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "0"
register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieRpAdvancedErrorReporting[5]" = "1"
register "pcie_rp_aspm[5]" = "AspmDisabled"
end
@ -181,7 +181,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[8]" = "0"
register "PcieRpHotPlug[8]" = "1"
register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "pcie_rp_aspm[8]" = "AspmDisabled"
end

2
src/mainboard/google/dedede/variants/awasuki/overridetree.cb
View file

@ -1,6 +1,6 @@
chip soc/intel/jasperlake
# PCIe RP LTR configuration
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
# USB Port Configuration
register "usb2_ports[1]" = "USB2_PORT_EMPTY"

2
src/mainboard/google/dedede/variants/drawcia/overridetree.cb
View file

@ -8,7 +8,7 @@ end
chip soc/intel/jasperlake
# PCIe RP LTR configuration
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
# USB Port Configuration
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera

4
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View file

@ -194,13 +194,13 @@ chip soc/intel/cannonlake
# PCIe port 9 for Card Reader
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[2]" = "12"
register "PcieClkSrcClkReq[2]" = "2"

4
src/mainboard/google/eve/devicetree.cb
View file

@ -340,7 +340,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpHotPlug[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"
chip drivers/wifi/generic
@ -353,7 +353,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "4"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpClkSrcNumber[4]" = "4"
end
device ref uart0 on end

12
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View file

@ -293,7 +293,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[2]" = "1"
register "PcieRpClkReqNumber[2]" = "0"
register "PcieRpAdvancedErrorReporting[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
register "PcieRpClkSrcNumber[2]" = "0"
chip drivers/net
register "customized_leds" = "0x0fa5"
@ -308,7 +308,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "5"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[3]" = "true"
register "PcieRpClkSrcNumber[3]" = "5"
chip drivers/wifi/generic
register "wake" = "GPE0_PCI_EXP"
@ -321,7 +321,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "1"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpClkSrcNumber[4]" = "1"
end
device ref pcie_rp9 on
@ -330,7 +330,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "2"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpClkSrcNumber[8]" = "2"
chip drivers/net
register "customized_leds" = "0x0fa5"
@ -343,7 +343,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[10]" = "1"
register "PcieRpClkReqNumber[10]" = "2"
register "PcieRpAdvancedErrorReporting[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
register "PcieRpClkSrcNumber[10]" = "2"
end
device ref pcie_rp12 on
@ -351,7 +351,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[11]" = "1"
register "PcieRpClkReqNumber[11]" = "2"
register "PcieRpAdvancedErrorReporting[11]" = "1"
register "PcieRpLtrEnable[11]" = "1"
register "PcieRpLtrEnable[11]" = "true"
register "PcieRpClkSrcNumber[11]" = "2"
end
device ref uart0 on end

6
src/mainboard/google/fizz/variants/endeavour/overridetree.cb
View file

@ -120,7 +120,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "4"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieRpClkSrcNumber[6]" = "4"
end
device ref pcie_rp8 on
@ -129,7 +129,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[7]" = "1"
register "PcieRpClkReqNumber[7]" = "2"
register "PcieRpAdvancedErrorReporting[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieRpClkSrcNumber[7]" = "2"
end
device ref pcie_rp9 on
@ -137,7 +137,7 @@ chip soc/intel/skylake
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "0"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpClkSrcNumber[8]" = "2"
end
device ref pcie_rp10 off

4
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View file

@ -163,7 +163,7 @@ chip soc/intel/cannonlake
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
# ClkReq-to-ClkSrc mapping for CLK SRC 1
@ -171,7 +171,7 @@ chip soc/intel/cannonlake
# PCIe port 14 for M.2 E-key WLAN
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
# RP 14 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "13"
register "PcieClkSrcClkReq[3]" = "3"

4
src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
View file

@ -21,7 +21,7 @@ chip soc/intel/cannonlake
# Enable Root port 9(x2) for NVMe.
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
# ClkReq-to-ClkSrc mapping for CLK SRC 1
@ -29,7 +29,7 @@ chip soc/intel/cannonlake
# Enable Root port 11(x2) for NVMe.
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# RP 11 uses CLK SRC 2
register "PcieClkSrcUsage[2]" = "10"
# ClkReq-to-ClkSrc mapping for CLK SRC 2

4
src/mainboard/google/hatch/variants/mushu/overridetree.cb
View file

@ -72,14 +72,14 @@ chip soc/intel/cannonlake
# PCIe port 7 for M.2 E-key WLAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# RP 7 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
# Enable Root port 13 (x4) for dGPU
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
# RP 13 uses CLK SRC 5
register "PcieClkSrcUsage[5]" = "12"
# ClkReq-to-ClkSrc mapping for CLK SRC 5

2
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View file

@ -315,7 +315,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_07" # GPP_B7
device pci 00.0 on end

2
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View file

@ -327,7 +327,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpClkSrcNumber[0]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_DW0_00"

6
src/mainboard/google/poppy/variants/nami/devicetree.cb
View file

@ -371,7 +371,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[3]" = "1"
register "PcieRpClkSrcNumber[3]" = "1"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[3]" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_DW2_22" # Wake pin = GPP_E22
device pci 00.0 on end
@ -384,7 +384,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
end
device ref pcie_rp9 on
# x2
@ -393,7 +393,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[8]" = "2"
register "PcieRpClkSrcNumber[8]" = "2"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
end
device ref uart0 on end
device ref gspi0 on

2
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View file

@ -366,7 +366,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_DW0_00"
device pci 00.0 on end

4
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View file

@ -330,7 +330,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_DW2_01"
device pci 00.0 on end
@ -343,7 +343,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[8]" = "2"
register "PcieRpClkSrcNumber[8]" = "3"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
end
device ref gspi0 on
chip drivers/spi/acpi

2
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View file

@ -319,7 +319,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_DW0_00" # GPP_B0
device pci 00.0 on end

2
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View file

@ -309,7 +309,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpClkSrcNumber[0]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_PCI_EXP"

4
src/mainboard/google/puff/variants/ambassador/overridetree.cb
View file

@ -185,10 +185,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

4
src/mainboard/google/puff/variants/baseboard/devicetree.cb
View file

@ -163,7 +163,7 @@ chip soc/intel/cannonlake
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
# ClkReq-to-ClkSrc mapping for CLK SRC 1
@ -171,7 +171,7 @@ chip soc/intel/cannonlake
# PCIe port 14 for M.2 E-key WLAN
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
# RP 14 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "13"
register "PcieClkSrcClkReq[3]" = "3"

2
src/mainboard/google/puff/variants/dooly/overridetree.cb
View file

@ -174,7 +174,7 @@ chip soc/intel/cannonlake
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

4
src/mainboard/google/puff/variants/duffy/overridetree.cb
View file

@ -246,10 +246,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

4
src/mainboard/google/puff/variants/faffy/overridetree.cb
View file

@ -254,10 +254,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

12
src/mainboard/google/puff/variants/genesis/overridetree.cb
View file

@ -178,21 +178,21 @@ chip soc/intel/cannonlake
# PCIe root port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
# Uses CLK SRC 5
register "PcieClkSrcUsage[5]" = "7"
register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcClkReq[1]" = "1"
@ -202,21 +202,21 @@ chip soc/intel/cannonlake
# PCIe root port 11 TPU1
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[4]" = "10"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0
register "PcieRpEnable[11]" = "true"
register "PcieRpLtrEnable[11]" = "1"
register "PcieRpLtrEnable[11]" = "true"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[2]" = "11"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4)
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
# RP 13 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "12"
# RP 13 does not use a source clock request line

4
src/mainboard/google/puff/variants/kaisa/overridetree.cb
View file

@ -246,10 +246,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

12
src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
View file

@ -178,21 +178,21 @@ chip soc/intel/cannonlake
# PCIe root port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
# Uses CLK SRC 5
register "PcieClkSrcUsage[5]" = "7"
register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcClkReq[1]" = "1"
@ -202,21 +202,21 @@ chip soc/intel/cannonlake
# PCIe root port 11 TPU1
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[4]" = "10"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0
register "PcieRpEnable[11]" = "true"
register "PcieRpLtrEnable[11]" = "1"
register "PcieRpLtrEnable[11]" = "true"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[2]" = "11"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4)
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
# RP 13 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "12"
# RP 13 does not use a source clock request line

4
src/mainboard/google/puff/variants/noibat/overridetree.cb
View file

@ -169,10 +169,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

4
src/mainboard/google/puff/variants/puff/overridetree.cb
View file

@ -179,10 +179,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

10
src/mainboard/google/puff/variants/scout/overridetree.cb
View file

@ -185,21 +185,21 @@ chip soc/intel/cannonlake
# PCIe root port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
# Uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe root port 9 for SSD (PCIe Lanes 9-12)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcClkReq[1]" = "1"
@ -211,14 +211,14 @@ chip soc/intel/cannonlake
# PCIe root port 13 TPU0
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
# RP 13 uses CLK SRC 2
register "PcieClkSrcUsage[2]" = "12"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe root port 14 TPU1
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
# RP 14 uses CLK SRC 4
register "PcieClkSrcUsage[4]" = "13"
register "PcieClkSrcClkReq[4]" = "4"

4
src/mainboard/google/puff/variants/wyvern/overridetree.cb
View file

@ -180,10 +180,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"

4
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View file

@ -188,13 +188,13 @@ chip soc/intel/cannonlake
# PCIe port 11 for card reader
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
register "PcieClkSrcUsage[1]" = "10"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[4]" = "12"
register "PcieClkSrcClkReq[4]" = "4"

4
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View file

@ -183,7 +183,7 @@ chip soc/intel/cannonlake
# PCIe port 8 for Card Reader
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieClkSrcUsage[4]" = "7"
register "PcieClkSrcClkReq[4]" = "4"
@ -199,7 +199,7 @@ chip soc/intel/cannonlake
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[2]" = "12"
register "PcieClkSrcClkReq[2]" = "2"

8
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View file

@ -425,14 +425,14 @@ chip soc/intel/tigerlake
end
device ref pcie_rp7 on
# WLAN PCIE 7 using clk 1
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
end
device ref pcie_rp8 on
# SD Card PCIE 8 using clk 3
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieRpHotPlug[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
@ -464,14 +464,14 @@ chip soc/intel/tigerlake
end
device ref pcie_rp9 on
# NVMe PCIE 9 using clk 0
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[8]" = "1"
end
device ref pcie_rp11 on
# Optane PCIE 11 using clk 0
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
register "HybridStorageMode" = "0"
register "PcieRpSlotImplemented[10]" = "1"
end

2
src/mainboard/google/volteer/variants/chronicler/overridetree.cb
View file

@ -268,7 +268,7 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# EMMC PCIE 5 using clk 5
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"

2
src/mainboard/google/volteer/variants/elemi/overridetree.cb
View file

@ -269,7 +269,7 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# EMMC PCIE 5 using clk 5
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"

4
src/mainboard/google/volteer/variants/voema/overridetree.cb
View file

@ -90,13 +90,13 @@ chip soc/intel/tigerlake
device ref pcie_rp7 off
# Disable WLAN PCIE 7
register "PcieRpLtrEnable[6]" = "0"
register "PcieRpLtrEnable[6]" = "false"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
register "PcieRpSlotImplemented[6]" = "1"
end
device ref pcie_rp8 off
# Disable SD Card PCIE 8
register "PcieRpLtrEnable[7]" = "0"
register "PcieRpLtrEnable[7]" = "false"
register "PcieRpHotPlug[7]" = "0"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
# override-devicetree rules say it's only

8
src/mainboard/hp/280_g2/devicetree.cb
View file

@ -65,7 +65,7 @@ chip soc/intel/skylake
device ref pcie_rp5 on
# IT8893E PCI Bridge
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpClkSrcNumber[4]" = "11"
end
@ -73,14 +73,14 @@ chip soc/intel/skylake
# PCIe x1 slot
register "PcieRpEnable[5]" = "1"
register "PcieRpHotPlug[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieRpAdvancedErrorReporting[5]" = "1"
register "PcieRpClkSrcNumber[5]" = "6"
end
device ref pcie_rp7 on
# RTL8111 GbE NIC
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpClkSrcNumber[6]" = "10"
end
@ -88,7 +88,7 @@ chip soc/intel/skylake
# M.2 2230 slot
register "PcieRpEnable[7]" = "1"
register "PcieRpHotPlug[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieRpAdvancedErrorReporting[7]" = "1"
register "PcieRpClkSrcNumber[7]" = "12"
end

8
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View file

@ -243,13 +243,13 @@ chip soc/intel/tigerlake
device ref pcie_rp2 off end
device ref pcie_rp3 on
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
register "PcieClkSrcUsage[1]" = "0x2"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp4 on
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[3]" = "true"
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3
@ -264,14 +264,14 @@ chip soc/intel/tigerlake
device ref pcie_rp8 off end
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[3]" = "0x8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 off end
device ref pcie_rp11 on
register "PcieRpSlotImplemented[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
end
device ref pcie_rp12 off end
device ref uart0 off end

8
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View file

@ -245,14 +245,14 @@ chip soc/intel/tigerlake
device ref pcie_rp2 off end
device ref pcie_rp3 on
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
register "PcieClkSrcUsage[1]" = "0x2"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp4 on
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[3]" = "true"
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3
@ -267,14 +267,14 @@ chip soc/intel/tigerlake
device ref pcie_rp8 off end
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[3]" = "0x8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 off end
device ref pcie_rp11 on
register "PcieRpSlotImplemented[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
end
device ref pcie_rp12 off end
device ref uart0 off end

4
src/mainboard/lenovo/m900_tiny/devicetree.cb
View file

@ -165,7 +165,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[16]" = "1"
register "PcieRpClkReqNumber[16]" = "1"
register "PcieRpAdvancedErrorReporting[16]" = "1"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "true"
register "PcieRpClkSrcNumber[16]" = "7"
register "PcieRpHotPlug[16]" = "1"
end
@ -174,7 +174,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "11"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieRpClkSrcNumber[6]" = "1"
register "PcieRpHotPlug[6]" = "1"
chip drivers/wifi/generic

20
src/mainboard/prodrive/hermes/devicetree.cb
View file

@ -172,7 +172,7 @@ chip soc/intel/cannonlake
device ref pcie_rp21 on
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieRpSlotImplemented[20]" = "1"
register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
register "PcieRpAdvancedErrorReporting[20]" = "1"
@ -181,7 +181,7 @@ chip soc/intel/cannonlake
device ref pcie_rp1 on
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpSlotImplemented[0]" = "1"
register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
register "PcieRpAdvancedErrorReporting[0]" = "1"
@ -189,28 +189,28 @@ chip soc/intel/cannonlake
end
device ref pcie_rp5 on # PHY 3
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
device pci 00.0 on
smbios_dev_info 3
end
end
device ref pcie_rp6 on # PHY 4
register "PcieRpEnable[5]" = "true"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
device pci 00.0 on
smbios_dev_info 4
end
end
device ref pcie_rp7 on # PHY 2
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
device pci 00.0 on
smbios_dev_info 2
end
end
device ref pcie_rp8 on # PHY 1
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
device pci 00.0 on
smbios_dev_info 1
end
@ -218,12 +218,12 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpSlotImplemented[8]" = "1"
end
device ref pcie_rp14 on # PHY 0
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
device pci 00.0 on
smbios_dev_info 0
end
@ -233,13 +233,13 @@ chip soc/intel/cannonlake
device pci 00.0 on end # Aspeed 2500 VGA
end
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "true"
register "PcieRpSlotImplemented[14]" = "1"
end
device ref pcie_rp16 on # M.2 E/CNVi
# Disabled when CNVi is present
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieRpLtrEnable[15]" = "true"
register "PcieRpSlotImplemented[15]" = "1"
end
device ref uart0 on end

16
src/mainboard/protectli/vault_cml/devicetree.cb
View file

@ -72,14 +72,14 @@ chip soc/intel/cannonlake
register "PcieRpAdvancedErrorReporting[12]" = "1"
# Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpLtrEnable[11]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpLtrEnable[5]" = "true"
register "PcieRpLtrEnable[6]" = "true"
register "PcieRpLtrEnable[7]" = "true"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpLtrEnable[9]" = "true"
register "PcieRpLtrEnable[11]" = "true"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"

14
src/mainboard/protectli/vault_kbl/devicetree.cb
View file

@ -144,49 +144,49 @@ chip soc/intel/skylake
# LAN
register "PcieRpEnable[0]" = "true"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpClkSrcNumber[0]" = "0"
end
device ref pcie_rp2 on
# LAN
register "PcieRpEnable[1]" = "true"
register "PcieRpAdvancedErrorReporting[1]" = "1"
register "PcieRpLtrEnable[1]" = "1"
register "PcieRpLtrEnable[1]" = "true"
register "PcieRpClkSrcNumber[1]" = "1"
end
device ref pcie_rp3 on
# LAN
register "PcieRpEnable[2]" = "true"
register "PcieRpAdvancedErrorReporting[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
register "PcieRpClkSrcNumber[2]" = "2"
end
device ref pcie_rp4 on
# LAN
register "PcieRpEnable[3]" = "true"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[3]" = "true"
register "PcieRpClkSrcNumber[3]" = "3"
end
device ref pcie_rp5 on
# LAN
register "PcieRpEnable[4]" = "true"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpClkSrcNumber[4]" = "4"
end
device ref pcie_rp6 on
# LAN
register "PcieRpEnable[5]" = "true"
register "PcieRpAdvancedErrorReporting[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieRpClkSrcNumber[5]" = "5"
end
device ref pcie_rp9 on
# mPCIe WIFI
register "PcieRpEnable[8]" = "true"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpClkSrcNumber[8]" = "5"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "0"

6
src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
View file

@ -127,7 +127,7 @@ chip soc/intel/cannonlake
device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN)
register "PcieRpEnable[6]" = "true"
register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieRpHotPlug[6]" = "1"
register "PcieClkSrcUsage[2]" = "6"
register "PcieClkSrcClkReq[2]" = "2"
@ -142,7 +142,7 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[8]" = "true"
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
@ -150,7 +150,7 @@ chip soc/intel/cannonlake
device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[12]" = "true"
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[1]" = "12"
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"

4
src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
View file

@ -119,7 +119,7 @@ chip soc/intel/cannonlake
device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN)
register "PcieRpSlotImplemented[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
register "PcieClkSrcUsage[2]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
@ -133,7 +133,7 @@ chip soc/intel/cannonlake
device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[1]" = "12"
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"

10
src/mainboard/purism/librem_l1um_v2/devicetree.cb
View file

@ -211,20 +211,20 @@ chip soc/intel/cannonlake
device ref pcie_rp21 on
register "PcieRpSlotImplemented[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieClkSrcUsage[10]" = "20"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
end
device ref pcie_rp1 on
register "PcieRpSlotImplemented[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieClkSrcUsage[1]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
end
device ref pcie_rp9 on # GbE #1
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[14]" = "8"
# Type indexes are needed for systemd to use "onboard" names by default
# (eno0, eno1). Otherwise it uses "slot" names that can change if any
@ -237,12 +237,12 @@ chip soc/intel/cannonlake
end
device ref pcie_rp10 on # BMC video
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "true"
register "PcieClkSrcUsage[8]" = "9"
end
device ref pcie_rp11 on # GbE #2
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
register "PcieClkSrcUsage[11]" = "10"
device pci 00.0 on
smbios_dev_info 2

6
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View file

@ -158,16 +158,16 @@ chip soc/intel/skylake
device ref pcie_rp1 on end
device ref pcie_rp3 on
register "PcieRpEnable[2]" = "true"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpHotPlug[4]" = "1"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"

2
src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
View file

@ -159,7 +159,7 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on # SSD x4
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[1]" = "0x08"
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"

4
src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
View file

@ -88,7 +88,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "4"
register "PcieRpClkSrcNumber[5]" = "4"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
chip drivers/wifi/generic
register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true"
@ -100,7 +100,7 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "0"
register "PcieRpClkSrcNumber[8]" = "0"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
device ref uart0 on end

10
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View file

@ -45,20 +45,20 @@ chip soc/intel/skylake
device ref pcie_rp1 on
# Slot JPCIE4
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpAdvancedErrorReporting[0]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref pcie_rp5 on
# Slot JPCIE5
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpAdvancedErrorReporting[4]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieRpAdvancedErrorReporting[8]" = "1"
device pci 00.0 on # GbE 1
subsystemid 0x15d9 0x1533
@ -66,7 +66,7 @@ chip soc/intel/skylake
end
device ref pcie_rp10 on
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "true"
register "PcieRpAdvancedErrorReporting[9]" = "1"
device pci 00.0 on # GbE 2
subsystemid 0x15d9 0x1533
@ -74,7 +74,7 @@ chip soc/intel/skylake
end
device ref pcie_rp11 on
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
register "PcieRpAdvancedErrorReporting[10]" = "1"
device pci 00.0 on # Aspeed PCI Bridge
device pci 00.0 on end # Aspeed 2400 VGA

12
src/mainboard/system76/addw1/devicetree.cb
View file

@ -99,7 +99,7 @@ chip soc/intel/cannonlake
device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "true"
register "PcieRpHotPlug[16]" = "1"
register "PcieClkSrcUsage[0]" = "16"
register "PcieClkSrcClkReq[0]" = "0"
@ -107,7 +107,7 @@ chip soc/intel/cannonlake
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 10 (SSD2)
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieClkSrcUsage[10]" = "20"
register "PcieClkSrcClkReq[10]" = "10"
register "PcieRpSlotImplemented[20]" = "1"
@ -115,7 +115,7 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 9 (SSD1)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[9]" = "8"
register "PcieClkSrcClkReq[9]" = "9"
register "PcieRpSlotImplemented[8]" = "1"
@ -123,7 +123,7 @@ chip soc/intel/cannonlake
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 5 (GLAN)
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
register "PcieClkSrcUsage[5]" = "13"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[13]" = "1"
@ -131,7 +131,7 @@ chip soc/intel/cannonlake
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 7 (Card Reader)
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "true"
register "PcieClkSrcUsage[7]" = "14"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieRpSlotImplemented[14]" = "1"
@ -139,7 +139,7 @@ chip soc/intel/cannonlake
device ref pcie_rp16 on
# PCI Express root port #16 x1, Clock 6 (WLAN)
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieRpLtrEnable[15]" = "true"
register "PcieClkSrcUsage[6]" = "15"
register "PcieClkSrcClkReq[6]" = "6"
register "PcieRpSlotImplemented[15]" = "1"

16
src/mainboard/system76/bonw14/devicetree.cb
View file

@ -114,21 +114,21 @@ chip soc/intel/cannonlake
device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 14 (SSD2)
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "true"
register "PcieClkSrcUsage[14]" = "16"
register "PcieClkSrcClkReq[14]" = "14"
end
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 15 (SSD3)
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieClkSrcUsage[15]" = "20"
register "PcieClkSrcClkReq[15]" = "15"
end
device ref pcie_rp1 on
# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpHotPlug[0]" = "1"
register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
register "PcieClkSrcClkReq[6]" = "6"
@ -136,35 +136,35 @@ chip soc/intel/cannonlake
device ref pcie_rp5 on
# PCI Express root port #5 x4, Clock 10 (USB 3.2)
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieClkSrcUsage[10]" = "4"
register "PcieClkSrcClkReq[10]" = "10"
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 8 (SSD)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[8]" = "8"
register "PcieClkSrcClkReq[8]" = "8"
end
device ref pcie_rp13 on
# PCI Express root port #13 x1, Clock 0 (WLAN)
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[0]" = "12"
register "PcieClkSrcClkReq[0]" = "0"
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 1 (GLAN)
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
register "PcieClkSrcUsage[1]" = "13"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 4 (Card Reader)
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "true"
register "PcieClkSrcUsage[4]" = "14"
register "PcieClkSrcClkReq[4]" = "4"
end

8
src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
View file

@ -41,7 +41,7 @@ chip soc/intel/cannonlake
device ref pcie_rp5 on
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
@ -49,21 +49,21 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "0"
register "PcieRpLtrEnable[9]" = "false"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp13 on
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
end

8
src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
View file

@ -34,7 +34,7 @@ chip soc/intel/cannonlake
device ref pcie_rp5 on
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
@ -42,21 +42,21 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "0"
register "PcieRpLtrEnable[9]" = "false"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp13 on
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
end

8
src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
View file

@ -42,7 +42,7 @@ chip soc/intel/cannonlake
device ref pcie_rp6 on
device pci 00.0 on end # x1 Card reader
register "PcieRpEnable[5]" = "true"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieClkSrcUsage[3]" = "5"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieRpSlotImplemented[5]" = "1"
@ -50,7 +50,7 @@ chip soc/intel/cannonlake
device ref pcie_rp8 on
device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieRpSlotImplemented[7]" = "1"
@ -62,7 +62,7 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[8]" = "1"
@ -71,7 +71,7 @@ chip soc/intel/cannonlake
device ref pcie_rp13 on
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[12]" = "1"

8
src/mainboard/system76/gaze15/devicetree.cb
View file

@ -97,7 +97,7 @@ chip soc/intel/cannonlake
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 11 (SSD2)
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieClkSrcUsage[11]" = "20"
register "PcieClkSrcClkReq[11]" = "11"
register "PcieRpSlotImplemented[20]" = "1"
@ -105,7 +105,7 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 10 (SSD)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[10]" = "8"
register "PcieClkSrcClkReq[10]" = "10"
register "PcieRpSlotImplemented[8]" = "1"
@ -113,7 +113,7 @@ chip soc/intel/cannonlake
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 6 (WLAN)
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
register "PcieClkSrcUsage[6]" = "13"
register "PcieClkSrcClkReq[6]" = "6"
register "PcieRpSlotImplemented[13]" = "1"
@ -121,7 +121,7 @@ chip soc/intel/cannonlake
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 5 (LAN)
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "true"
register "PcieClkSrcUsage[5]" = "14"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[14]" = "1"

8
src/mainboard/system76/kbl-u/devicetree.cb
View file

@ -138,7 +138,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "4"
register "PcieRpClkSrcNumber[0]" = "4"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
register "PcieRpHotPlug[0]" = "1"
end
device ref pcie_rp5 on
@ -148,7 +148,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
end
device ref pcie_rp6 on
# Root port #6 x1 (WLAN)
@ -157,7 +157,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[5]" = "2"
register "PcieRpClkSrcNumber[5]" = "2"
register "PcieRpAdvancedErrorReporting[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
end
device ref pcie_rp9 on
# Root port #9 x4 (NVMe)
@ -166,7 +166,7 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[8]" = "5"
register "PcieRpClkSrcNumber[8]" = "5"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"

10
src/mainboard/system76/oryp5/devicetree.cb
View file

@ -110,35 +110,35 @@ chip soc/intel/cannonlake
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 11 (SSD2)
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieClkSrcUsage[11]" = "20"
register "PcieClkSrcClkReq[11]" = "11"
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 12 (SSD)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[12]" = "8"
register "PcieClkSrcClkReq[12]" = "12"
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 13 (WLAN)
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
register "PcieClkSrcUsage[13]" = "13"
register "PcieClkSrcClkReq[13]" = "13"
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 14 (GLAN)
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "true"
register "PcieClkSrcUsage[14]" = "14"
register "PcieClkSrcClkReq[14]" = "14"
end
device ref pcie_rp16 on
# PCI Express root port #16 x1, Clock 15 (Card Reader)
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieRpLtrEnable[15]" = "true"
register "PcieClkSrcUsage[15]" = "15"
register "PcieClkSrcClkReq[15]" = "15"
end

12
src/mainboard/system76/oryp6/devicetree.cb
View file

@ -107,7 +107,7 @@ chip soc/intel/cannonlake
device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "true"
register "PcieRpHotPlug[16]" = "1"
register "PcieClkSrcUsage[0]" = "16"
register "PcieClkSrcClkReq[0]" = "0"
@ -116,7 +116,7 @@ chip soc/intel/cannonlake
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 11 (SSD2)
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieClkSrcUsage[11]" = "20"
register "PcieClkSrcClkReq[11]" = "11"
register "PcieRpSlotImplemented[20]" = "1"
@ -124,7 +124,7 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 12 (SSD1)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[12]" = "8"
register "PcieClkSrcClkReq[12]" = "12"
register "PcieRpSlotImplemented[8]" = "1"
@ -132,7 +132,7 @@ chip soc/intel/cannonlake
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 7 (GLAN)
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "true"
register "PcieClkSrcUsage[7]" = "13"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieRpSlotImplemented[13]" = "1"
@ -140,7 +140,7 @@ chip soc/intel/cannonlake
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 9 (Card Reader)
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "true"
register "PcieClkSrcUsage[9]" = "14"
register "PcieClkSrcClkReq[9]" = "9"
register "PcieRpSlotImplemented[14]" = "1"
@ -148,7 +148,7 @@ chip soc/intel/cannonlake
device ref pcie_rp16 on
# PCI Express root port #16 x1, Clock 6 (WLAN)
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieRpLtrEnable[15]" = "true"
register "PcieClkSrcUsage[6]" = "15"
register "PcieClkSrcClkReq[6]" = "6"
register "PcieRpSlotImplemented[15]" = "1"

8
src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
View file

@ -55,26 +55,26 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 5 (GLAN)
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 7 (CARD)
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieClkSrcUsage[7]" = "6"
register "PcieClkSrcClkReq[7]" = "7"
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 8 (WLAN)
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieClkSrcUsage[8]" = "7"
register "PcieClkSrcClkReq[8]" = "8"
register "PcieRpSlotImplemented[7]" = "1"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 9 (SSD1)
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[9]" = "8"
register "PcieClkSrcClkReq[9]" = "9"
register "PcieRpSlotImplemented[8]" = "1"

8
src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
View file

@ -55,26 +55,26 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 8 (GLAN)
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
#register "PcieClkSrcUsage[8]" = "4"
register "PcieClkSrcClkReq[8]" = "8"
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 3 (CARD)
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 2 (WLAN)
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieRpSlotImplemented[7]" = "1"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 10 (SSD2)
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[10]" = "8"
register "PcieClkSrcClkReq[10]" = "10"
register "PcieRpSlotImplemented[8]" = "1"

8
src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
View file

@ -64,26 +64,26 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 8 (GLAN)
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieClkSrcUsage[8]" = "4"
register "PcieClkSrcClkReq[8]" = "8"
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 10 (CARD)
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieClkSrcUsage[10]" = "5"
register "PcieClkSrcClkReq[10]" = "10"
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 2 (WLAN)
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieRpSlotImplemented[7]" = "1"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 6 (SSD2)
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[6]" = "8"
register "PcieClkSrcClkReq[6]" = "6"
register "PcieRpSlotImplemented[8]" = "1"

10
src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
View file

@ -139,17 +139,17 @@ chip soc/intel/tigerlake
register "SataSalpSupport" = "1"
end
device ref pcie_rp1 on
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "true"
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 2 (CARD)
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 3 (GLAN)
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
chip soc/intel/common/block/pcie/rtd3
@ -161,14 +161,14 @@ chip soc/intel/tigerlake
end
device ref pcie_rp8 on
# PCIe root port #8 x1, Clock 1 (WLAN)
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "true"
register "PcieClkSrcUsage[1]" = "7"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[7]" = "1"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 4 (SSD0)
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[8]" = "1"

8
src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
View file

@ -143,7 +143,7 @@ chip soc/intel/tigerlake
end
device ref pcie_rp5 on
# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieClkSrcUsage[2]" = "4"
register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3
@ -159,13 +159,13 @@ chip soc/intel/tigerlake
end
device ref pcie_rp9 on
# PCIe root port #9 x1, Clock 3 (CARD)
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCIe root port #10 x1, Clock 4 (GLAN)
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "true"
register "PcieClkSrcUsage[4]" = "9"
register "PcieClkSrcClkReq[4]" = "4"
chip soc/intel/common/block/pcie/rtd3
@ -177,7 +177,7 @@ chip soc/intel/tigerlake
end
device ref pcie_rp11 on
# PCIe root port #11 x1, Clock 1 (WLAN)
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
register "PcieClkSrcUsage[1]" = "10"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[10]" = "1"

6
src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
View file

@ -120,21 +120,21 @@ chip soc/intel/tigerlake
end
device ref pcie_rp3 on
# PCIe root port #3 x1, Clock 1 (WLAN)
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[2]" = "true"
register "PcieClkSrcUsage[1]" = "2"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[2]" = "1"
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 2 (CARD)
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "true"
register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 0 (SSD2)
# Despite the name, SSD1_CLKREQ# is used for SSD2
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[8]" = "1"

8
src/mainboard/system76/whl-u/devicetree.cb
View file

@ -100,7 +100,7 @@ chip soc/intel/cannonlake
device ref pcie_rp5 on
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "true"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
@ -108,21 +108,21 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "0"
register "PcieRpLtrEnable[9]" = "false"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp13 on
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "true"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
end

4
src/soc/intel/jasperlake/chip.h
View file

@ -152,8 +152,8 @@ struct soc_intel_jasperlake_config {
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR */
bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];

6
src/soc/intel/skylake/chip.h
View file

@ -201,11 +201,7 @@ struct soc_intel_skylake_config {
*/
bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
/*
* Enable/Disable Latency Tolerance Reporting for Root Port
* 0: Disable LTR
* 1: Enable LTR
*/
/* Enable/Disable Latency Tolerance Reporting for Root Port */
bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* Enable/Disable HotPlug support for Root Port */

4
src/soc/intel/tigerlake/chip.h
View file

@ -277,8 +277,8 @@ struct soc_intel_tigerlake_config {
/* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR */
bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];

4
util/mainboard/google/puff/template/overridetree.cb
View file

@ -184,10 +184,10 @@ chip soc/intel/cannonlake
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "true"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "true"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"