soc/intel/pantherlake: Add support for VMD device

This commit adds support for VMD (Volume Management Device) in the
Panther Lake SoC. VMD is a feature that allows the management of NVMe
storage devices by abstracting the PCIe root complex. It provides a way
to manage multiple NVMe drives more efficiently.

Changes include:
- Adding VMD to the `min_pci_sleep_states` array in `acpi.c`.
- Updating `chipset.cb` to include the VMD device.
- Disabling the VMD device by default.
- Introducing a new function `fill_fsps_vmd_params`.
- Defining the VMD device and function numbers in `pci_devs.h`.

BUG=b:391083063
TEST=Able to build and boot google/fatcat. Observed that VmdEnable UPD
     is disabled in debug FSP logs.

Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>

src/soc/intel/pantherlake/acpi.c

@@ -193,6 +193,7 @@ static struct min_sleep_state min_pci_sleep_states[] = {
 	{ PCI_DEVFN_TCSS_XDCI,	ACPI_DEVICE_SLEEP_D3 },
 	{ SA_DEVFN_TCSS_DMA0,	ACPI_DEVICE_SLEEP_D3 },
 	{ SA_DEVFN_TCSS_DMA1,	ACPI_DEVICE_SLEEP_D3 },
+	{ PCI_DEVFN_VMD,        ACPI_DEVICE_SLEEP_D3 },
 	{ PCI_DEVFN_THC0,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCI_DEVFN_THC1,	ACPI_DEVICE_SLEEP_D3 },
 	{ PCH_DEVFN_XHCI,	ACPI_DEVICE_SLEEP_D3 },

src/soc/intel/pantherlake/chipset.cb

@@ -86,6 +86,7 @@ chip soc/intel/pantherlake
 		device pci 0d.1 alias tcss_xdci off end
 		device pci 0d.2 alias tcss_dma0 off end
 		device pci 0d.3 alias tcss_dma1 off end
+		device pci 0e.0 alias vmd off end
 		device pci 10.0 alias thc0 off end
 		device pci 10.1 alias thc1 off end
 		device pci 12.0 alias ish off end

src/soc/intel/pantherlake/fsp_params.c

@@ -560,6 +560,12 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->CnviBtInterface = is_devfn_enabled(PCI_DEVFN_CNVI_BT) ? 2 : 1;
 }
 
+static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg,
+				 const struct soc_intel_pantherlake_config *config)
+{
+	s_cfg->VmdEnable = is_devfn_enabled(PCI_DEVFN_VMD);
+}
+
 static void fill_fsps_pmcpd_params(FSP_S_CONFIG *s_cfg,
 				   const struct soc_intel_pantherlake_config *config)
 {
@@ -710,6 +716,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		fill_fsps_pci_ssid_params,
 		fill_fsps_lan_params,
 		fill_fsps_cnvi_params,
+		fill_fsps_vmd_params,
 		fill_fsps_pmcpd_params,
 		fill_fsps_thc_params,
 		fill_fsps_8254_params,

src/soc/intel/pantherlake/include/soc/pci_devs.h

@@ -79,6 +79,10 @@
 #define  PCI_DEV_TCSS_DMA0	_PCI_DEV(TCSS, 2)
 #define  PCI_DEV_TCSS_DMA1	_PCI_DEV(TCSS, 3)
 
+#define PCI_DEV_SLOT_VMD	0x0e
+#define  PCI_DEVFN_VMD		_PCI_DEVFN(VMD, 0)
+#define  PCI_DEV_VMD		_PCI_DEV(VMD, 0)
+
 #define PCI_DEV_SLOT_THC	0x10
 #define  PCI_DEVFN_THC0		_PCI_DEVFN(THC, 0)
 #define  PCI_DEVFN_THC1		_PCI_DEVFN(THC, 1)