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soc/intel/meteorlake: Add missing USB port definitions

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The TCSS_XHCI controller has a single USB2 port followed by 4 USB3
ports; the XHCI controller has 12 USB2 ports followed by 2 USB3
ports. The topology was queried from the root hub on each controller
and returned via the descriptor.

Add the 2 missing USB2 ports to the XHCI controller and the one to
the TSS_XHCI controller.

TEST=build/boot Win11, Linux 6.x on starlabs/starbook_mtl.

Change-Id: I5dc97f150ff064d55e7969f10c1cea8ba72d6bfb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit is contained in:
Matt DeVillier 2025-02-06 21:00:10 -06:00
commit cd414d9d61
1 changed files with 9 additions and 0 deletions
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9
src/soc/intel/meteorlake/chipset.cb
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@ -69,6 +69,9 @@ chip soc/intel/meteorlake
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
device usb 0.0 alias tcss_root_hub off
chip drivers/usb/acpi
device usb 2.0 alias tcss_usb2_port1 off end
end
chip drivers/usb/acpi
device usb 3.0 alias tcss_usb3_port0 off end
end
@ -131,6 +134,12 @@ chip soc/intel/meteorlake
chip drivers/usb/acpi
device usb 2.9 alias usb2_port10 off end
end
chip drivers/usb/acpi
device usb 2.a alias usb2_port11 off end
end
chip drivers/usb/acpi
device usb 2.b alias usb2_port12 off end
end
chip drivers/usb/acpi
device usb 3.0 alias usb3_port1 off end
end