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soc/intel/tigerlake: Change the maximum C state to C8

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The EDS says that Tiger Lake "supports C0, C2, C3, C6, C8,
and C10 package states". Update the highest state for non-S0ix
boards accordingly.

Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86199
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2025-01-28 17:01:33 +00:00
commit b03f85f3a2
1 changed files with 1 additions and 1 deletions
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src/soc/intel/tigerlake/acpi.c
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@ -102,7 +102,7 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
static int cstate_set_non_s0ix[] = {
C_STATE_C1,
C_STATE_C6_LONG_LAT,
C_STATE_C7S_LONG_LAT
C_STATE_C8
};
static int cstate_set_s0ix[] = {