dptf_enable is a boolean, so use true false instead of 0 1.
Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86183
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Define the generic cbmem_top_chipset() in the driver code, which will
invoke a SoC-specific vendorcode openSIL call to retrieve the low
usable DRAM address.
Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Refactor to factor out and route ACPI calls through the openSIL driver
interface to separate main SoC code from vendorcode.
Change-Id: I9fa4f60164333ec7a268702fa3e94979a1b83594
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The google/fatcat board's flash layout was modified to increase the
size of RW_SECTION_A and RW_SECTION_B by 1MB each (from 7MB to 8MB).
The RW_UNUSED region size was reduced to accommodate the increased
RW_SECTION sizes.
This change provides additional space in the RW slots to accommodate
growth in the payload (depthcharge).
TEST=Built and flashed the image. Verified that both RW_SECTION_A and
RW_SECTION_B are populated with the correct firmware components and
that the system boots successfully.
Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This moves the FPS device from GSPI0A to GSPI0 to align with the
hardware design dated Jan'25.
The FPS device was initially placed on GSPI0A, which was incorrect. This
commit rectifies the configuration by moving it to the correct GSPI0
interface.
This change ensures that the CRFP device is correctly connected and
functions as expected.
BUG=b:377595986
TEST=Able to build and boot google/fatcat.
Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86143
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EC_DASHARO_EC_FLASH_SIZE is set regardless of whether the dasharo
EC is used. Add a dependency so it is only set when needed.
Change-Id: Icce0c7a31c89cea5e7bf89770dedbf82ff56170b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Guard the Hyper-Threading option against SOC_INTEL_ALDERLAKE_PCH_N,
as the N200 processors used don't support it.
Change-Id: Ia30a14bd652bf8f2abad5fb5c19aed1cad694929
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86166
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If S0ix is not enabled, then it should not be reported that it
is supported.
TEST=boot linux on starlabs boards, check s2idle isn't
listed under `/sys/power/mem_sleep`.
Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86133
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Set mcufw_reserved region to non-cacheable and remove cache operation in
dvfs.c.
TEST=Build pass, boot ok.
Check MMU List by CVD (Codeviser):
0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable
BUG=b:390334489
Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86159
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit adds the Panther Lake Intel Dynamic Tuning
Technology (Intel DTT) PCI Device ID to the list of supported devices
in the ACPI Common Block DTT driver.
The Panther Lake Intel DTT PCI ID is defined in document #815002,
"Panther Lake U/H Processor - External Design Specification - Volume
1".
TEST=The SSDT ACPI table includes the DPTF device definition on
fatcat board.
Change-Id: Ia8dbe86efdf341a629de037d37750b79395ec3e8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This will configure CpuCrashLogEnable regardless of Tracehub
configuration as Crashlog feature does not have a dependency
with Tracehub.
TEST=Build fatcat and check Crashlog is enabled without enabling
Tracehub.
Change-Id: I6f37e9f4a1f55ffc576af955c92d4073068eb97a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85614
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
It seems that this is needed for specific drives, specifically,
the WD Black SN770.
Change-Id: Ibade3043489b82e5308231472dfe2c629b591661
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit b3718dee9c.
It seems that this is needed for specific drives, specifically,
the WD Black SN770.
Change-Id: I5ac2ea7978fca455d39fc7663e5cb219f3f8746f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There are no resources to allocate for LDN 0, so drop it to eliminate
a spurious cbmem log error (PNP 4e.00: missing read resources).
Change-Id: I6d9c3982b128e1480bc0948e19825465274dd769
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently, the eDP panel has display shift issue. This issue
is caused by too short HS-trail time.
Based on hardware design ANX7625 requires more HS-trail time to
finish mipi data packet decoding before entering LP mode.
So increase HS-trail time to avoid effect of entering LP mode.
da_hs_trail value copy from "kukui/panel_anx7625.c", verified
on corsola.
BUG=b:391304679
BRANCH=corsola
TEST=Display is normal on corsola
Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57
Signed-off-by: Xin Ji <xji@analogix.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86101
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Create the pujjoniru variant of the nissa reference board by copying
the template files to a new directory named for the variant.
And based on schematics PujjoNiru_C5_CHROME_TWL_SCH_MB_V1_1225A.pdf
update devicetree settings.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:386221423
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJONIRU
Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85844
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
These pads are required for Audio Offload, so enable them to match
the configuration in devicetree.
Change-Id: Icbe68adc24c18b089ff1559597bfcb74aead2a60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86129
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is using the USB interface for Bluetooth so these
can be disabled.
Change-Id: Iee80595e9e7d0652a723d44b11d9dc7a1c79417a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
BT_EN (VGPIO_0) needs to be host-owned, so that the driver
can control it during the reset procedure. Adjust it accordingly.
Change-Id: I13ac7a31f1518450fc6d8feefb9f37115e4628a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is used as MODEM_CLKREQ, which is Native Function 1.
Adjust the configuration accordingly.
Change-Id: Icc8be62e620a3e51826fb7c2c040da317e7eb470
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not every board will use CNVi, so move this out of the chipset.cb
and into devicetree.
Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If S0ix is not enabled, then it should not be reported that it
is supported.
TEST=boot linux on starlabs/starlite_adl, check s2idle isn't
listed under `/sys/power/mem_sleep`.
Change-Id: Ia31fbfd0b9795990b0ca98220bb002bf2c3857b2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This allows controlling the FSP debug log level using CBFS RAW binary
files, providing more flexibility in debugging silicon firmware issues
with a debug AP FW binary.
The following CBFS files are used to determine the log levels:
- fsp_pcd_debug_level: For the overall FSP debug log level.
- fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log
level.
This capability is particularly useful when debugging issues that
require examining both silicon and MRC logs simultaneously.
BUG=b:227151510
TEST=Able to control the FSP debug log based on CBFS options
To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files
with the desired log level, run:
```
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level
```
Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86002
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit relies on newly added Kconfig option,
USE_CBFS_FILE_OPTION_BACKEND, which allows controlling the FSP debug
log level using CBFS options (RAW binary files).
The default log-level is setup in coreboot while stitching the CBFS
option binaries depending upon the coreboot log-level.
Following files will be used to determine the log levels:
- fsp_pcd_debug_level: For the overall FSP debug log level.
- fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log
level.
In absense of these files, the FSP console log-level is determine by
calling into fsp_map_console_log_level API.
The values in these files should correspond to the FSP_LOG_LEVEL_* enum
values.
This change allows for more flexibility in controlling the FSP debug log
level, especially in cases of debugging silicon firmware issues with a
debug AP FW binary.
This capability is particularly useful when debugging issues that
require examining both silicon and MRC logs simultaneously.
BUG=b:227151510
TEST=Able to control the FSP debug log based on CBFS options
To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files
with the desired log level, run:
```
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level
```
With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO
CBFS, both the silicon firmware and MRC behave as debug binaries.
To verify the presence of both log-level RAW CBFS binaries in the CBFS RO
slot, run:
```
sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_
```
This should output:
```
option/fsp_mrc_debug_level 0x88e40 raw 8 none
option/fsp_pcd_debug_level 0x2a7400 raw 8 none
```
Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86001
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Adjust the allocated region size for mcufw_reserved from 52K to 68K.
TEST=Build pass.
BUG=b:390334489
Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change fixes CRC calculations in cases where an expression
calculating the address using pointer arithmetic is passed into the
macro.
Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86099
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4
BUG=b:387056119
BRANCH=none
TEST=built firmware and verified by power team, and noise pass.
Change-Id: I57055cdfc9377ba141c620dd4e9301f6e7601629
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86103
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Update the HDA verb table to remove the location setting
for uldrenite.
BUG=b:374203133
TEST=emerge-nissa coreboot
Change-Id: I05767ac80c2e3d609f944d0f669fcb343c1991ef
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86079
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the GPIO pin(GPP_B18) configuration issue base on schematic.
TCHSCR_REPORT_DISABLE(GPP_B18):
Low : Enable
High : Disable
BUG=b:391720235
TEST=Build and boot to OS in francka. Touch screen is workable.
Change-Id: Iba26f496176c2e406285df323e3da3e861fa2ffc
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86117
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This default configuration caused a problem where USB devices connected
behind a powered hub and/or Servo v4.1 were not detected.
Reverting this change restores the previous behavior where Trace Hub
and DCI are disabled by default, resolving the USB detection issue.
BUG=b:384453901
TEST=Able to boot google/fatcat using USB storage behind servo v4.1
This reverts commit 1ed186fbff84386e0196dd30dd7bc89b8fec2cec.
Change-Id: I1a0f66d7ddf84622820f82c559d7d6b846ba3a7d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86105
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Previously, DCI was enabled unconditionally, which could interfere with
the USB data path when connected behind a powered hub and/or servo v4.1
debug connector.
This patch sets DciEn parameter based on the selected platform debug
option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is
set to 0.
BUG=b:384453901
TEST=Able to boot google/fatcat.
Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
When the CFLR method was added, it was inadvertently put outside of the
scope of the CNVW device. Move CFLR under CNVW, and adjust the method/
variable references as needed.
TEST=boot linux, dump ACPI, verify no unknown methods or objects
related to the CNVW device.
Change-Id: I7065e24626b2f763868909b8f85a8f18b4cc229b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86092
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This method is used in the Intel/AMI reference code to verify
that the device is present (vendor ID != 0xFFFFFFFF), but that's
neither used nor needed here, as coreboot only generates SSDT
code for devices which are actually present.
TEST=build/boot Linux, verify no ACPI issues after dropping
Change-Id: Ib60c48852923e965620f4eee6a886c8c0f5c1783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86091
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Enable RTC so that we can see the correct timestamp and date in
ChromeOS.
rauru-rev0 ~ # tail /var/log/eventtlog.txt
suspend_stress_test -c 5 --suspend_max=30 --suspend_min=30
rauru-rev0 ~ # date
Thu Nov 7 14:54:09 CST 2024
TEST=Build pass, check date in ChromeOS
BUG=b:355550460
Change-Id: I95822fc7646d41dbbc61258741a2a42988fc31d7
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Zynq 7000 family of SoCs integrates up to two Cortex-A9 processor
cores with FPGA fabric using Xilinx's 7-series architecture. This commit
adds the bare minimum support code to compile a rom successfully when
the SoC is selected by a board. This code was loosely based on the TI
AM335x code, especially the memlayout.ld file.
In its current state valid Zynq boot images cannot be produced. CBFS
media is not yet supported so only the bootblock is able to run. The
easiest way to run this code is to manually load the bootblock ELF into
memory over JTAG using OpenOCD.
Change-Id: I45aa4e3a11074fa447d4008ac3c96d44f891831c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Some newer boards (like google/skyrim) use a separate line for each
field, so adjust parsing to accommodate that.
TEST=run `bash crosfirmware.sh` for frostflow, grunt, careena.
Change-Id: I3af38d3577f1390c999ad5e6df0fa2c4c4382245
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
These definitions are no longer necessary, since macros from
intel/common are used in the configuration [1].
[1] CB:42914
Change-Id: I0a6061aa562ea98c1bcffd86adac9aea28d7766b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84336
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds new macros to configure the pad in bidirectional mode when both
(Tx/Rx) buffers are enabled in the configuration register DW0. This
corresponds to FSP's < GpioDirInOut > parameter for port direction
(for example see config for SOUTH_GROUP0_DFX_SPARE2 pad in
src/mainboard/intel/harcuvar/gpio.h).
This macro is used in the pad configuration for some boards:
CB:43456 - mb/intel/cedarisland_crb;
CB:39133 - mb/kontron/mal10;
CB:43410 - mb/51nb/x210;
CB:43411 - mb/razer/blade_stealth_kbl.
Change-Id: I7b65f4da7616f2eefcd33a728d4d3ae5a79b014e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42914
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Intel's recommendation for Time Coordinated Computing (TCC)
the FSP-S parameter PchLegacyIoLowLatency should be set to 'Enabled'
in order to promote low latencies on the PCH.
With the previous setting 'Disabled' low latencies on the PCH for
I/O operations are not enhanced.
Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86068
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
