tree: Use true, false for dptf_enable

dptf_enable is a boolean, so use true false instead of 0 1.

Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86183
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>

src/mainboard/51nb/x210/devicetree.cb

@@ -27,7 +27,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Disable DPTF
-	register "dptf_enable" = "0"
+	register "dptf_enable" = "false"
 
 	# FSP Configuration
 	register "DspEnable" = "0"

src/mainboard/aoostar/wtr_r1/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/alderlake
 
 	register "sagv" = "SaGv_Enabled"
 
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "s0ix_enable" = "true"
 

src/mainboard/asrock/h110m/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# FSP Configuration
 	register "PrimaryDisplay" = "Display_PEG"

src/mainboard/facebook/monolith/devicetree.cb

@@ -22,7 +22,7 @@ chip soc/intel/skylake
 	register "eist_enable" = "true"
 
 	# DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# FSP Configuration
 	register "ScsEmmcHs400Enabled" = "1"

src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb

@@ -25,7 +25,7 @@ chip soc/intel/alderlake
 	register "disable_c1_state_auto_demotion" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "10"     # TCC of 90
 

src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "10"     # TCC of 90
 

src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb

@@ -19,7 +19,7 @@ chip soc/intel/alderlake
 	register "disable_package_c_state_demotion" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "10"     # TCC of 90
 

src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "10"     # TCC of 90
 

src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

@@ -32,7 +32,7 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "10"     # TCC of 90
 

src/mainboard/google/brya/variants/orisa/overridetree.cb

@@ -23,7 +23,7 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "10"     # TCC of 90
 

src/mainboard/google/brya/variants/trulo/overridetree.cb

@@ -23,7 +23,7 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "10"     # TCC of 90
 

src/mainboard/google/brya/variants/uldrenite/overridetree.cb

@@ -5,7 +5,7 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "true"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "tcc_offset" = "5"     # TCC of 100
 

src/mainboard/google/dedede/variants/baseboard/devicetree.cb

@@ -159,7 +159,7 @@ chip soc/intel/jasperlake
 	register "DdiPortCDdc" = "1"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Power limit config
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -40,7 +40,7 @@ chip soc/intel/cannonlake
 	register "PchUsb2PhySusPgDisable" = "1"
 
 	register "s0ix_enable" = "true"
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 51,

src/mainboard/google/eve/devicetree.cb

@@ -184,7 +184,7 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 7,
 		.tdp_pl2_override = 15,

src/mainboard/google/fizz/variants/baseboard/devicetree.cb

@@ -53,7 +53,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/glados/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# FSP Configuration
 	register "DspEnable" = "1"

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -30,7 +30,7 @@ chip soc/intel/cannonlake
 	# Enable S0ix
 	register "s0ix_enable" = "true"
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 64,

src/mainboard/google/octopus/variants/baseboard/devicetree.cb

@@ -55,7 +55,7 @@ chip soc/intel/apollolake
 	register "lpss_s0ix_enable" = "true"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable Audio Clock and Power gating
 	register "hdaudio_clk_gate_enable" = "1"

src/mainboard/google/poppy/variants/atlas/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -19,7 +19,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/poppy/variants/nami/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/poppy/variants/nocturne/devicetree.cb

@@ -21,7 +21,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/poppy/variants/rammus/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable S0ix
 	register "s0ix_enable" = true

src/mainboard/google/puff/variants/baseboard/devicetree.cb

@@ -30,7 +30,7 @@ chip soc/intel/cannonlake
 	# Enable S0ix
 	register "s0ix_enable" = "true"
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 64,

src/mainboard/google/reef/variants/baseboard/devicetree.cb

@@ -46,7 +46,7 @@ chip soc/intel/apollolake
 	register "emmc_rx_cmd_data_cntl2" = "0x10008"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# PL1 override 12 W: the energy calculation is wrong with the
 	# current VR solution. Experiments show that SoC TDP max (6W) can

src/mainboard/google/reef/variants/coral/devicetree.cb

@@ -46,7 +46,7 @@ chip soc/intel/apollolake
 	register "emmc_rx_cmd_data_cntl2" = "0x10008"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# PL1 override 12 W: the energy calculation is wrong with the
 	# current VR solution. Experiments show that SoC TDP max (6W) can

src/mainboard/google/reef/variants/pyro/devicetree.cb

@@ -46,7 +46,7 @@ chip soc/intel/apollolake
 	register "emmc_rx_cmd_data_cntl2" = "0x10008"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# PL1 override 12 W: the energy calculation is wrong with the
 	# current VR solution. Experiments show that SoC TDP max (6W) can

src/mainboard/google/reef/variants/sand/devicetree.cb

@@ -43,7 +43,7 @@ chip soc/intel/apollolake
 	register "emmc_rx_cmd_data_cntl2" = "0x10008"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# PL1 override 12 W: the energy calculation is wrong with the
 	# current VR solution. Experiments show that SoC TDP max (6W) can

src/mainboard/google/reef/variants/snappy/devicetree.cb

@@ -46,7 +46,7 @@ chip soc/intel/apollolake
 	register "emmc_rx_cmd_data_cntl2" = "0x10008"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# PL1 override 12 W: the energy calculation is wrong with the
 	# current VR solution. Experiments show that SoC TDP max (6W) can

src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb

@@ -45,7 +45,7 @@ chip soc/intel/meteorlake
 	register "pch_pm_energy_report_enable" = "1"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10)
 	register "tcc_offset" = "10"

src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb

@@ -43,7 +43,7 @@ chip soc/intel/meteorlake
 	register "pch_pm_energy_report_enable" = "1"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10)
 	register "tcc_offset" = "10"

src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb

@@ -45,7 +45,7 @@ chip soc/intel/meteorlake
 	register "pch_pm_energy_report_enable" = "1"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
 	register "tcc_offset" = "10"

src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb

@@ -43,7 +43,7 @@ chip soc/intel/meteorlake
 	register "pch_pm_energy_report_enable" = "1"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -28,7 +28,7 @@ chip soc/intel/cannonlake
 	register "PchUsb2PhySusPgDisable" = "1"
 
 	register "s0ix_enable" = "true"
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 	register "satapwroptimize" = "1"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 25,

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -31,7 +31,7 @@ chip soc/intel/cannonlake
 	register "PchUsb2PhySusPgDisable" = "1"
 
 	register "s0ix_enable" = "true"
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 	register "satapwroptimize" = "1"
 	register "AcousticNoiseMitigation" = "1"
 	register "SlowSlewRateForIa" = "2"

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -198,7 +198,7 @@ chip soc/intel/tigerlake
 	register "s0ix_enable" = "true"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Enable External Bypass
 	register "external_bypass" = "1"

src/mainboard/intel/adlrvp/devicetree.cb

@@ -133,7 +133,7 @@ chip soc/intel/alderlake
 	register "tcss_aux_ori" = "0"
 
 	register "s0ix_enable" = "true"
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,

src/mainboard/intel/adlrvp/devicetree_n.cb

@@ -17,7 +17,7 @@ chip soc/intel/alderlake
 	register "sagv" = "SaGv_Enabled"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# eMMC HS400
 	register "emmc_enable_hs400_mode" = "true"

src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb

@@ -49,7 +49,7 @@ chip soc/intel/apollolake
 	register "emmc_tx_cmd_cntl" = "0x1305"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# PL1 override: 7.5W setting gives a run-time 6W actual
 	# Set RAPL PL2 to 15W.

src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb

@@ -116,7 +116,7 @@ chip soc/intel/jasperlake
 	}"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Add PL1 and PL2 values
 	register "power_limits_config[JSL_N4500_6W_CORE]" = "{

src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb

@@ -14,7 +14,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# FSP Configuration
 	register "IoBufferOwnership" = "0"

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -14,7 +14,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# FSP Configuration
 	register "DspEnable" = "1"

src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb

@@ -115,7 +115,7 @@ chip soc/intel/meteorlake
 	register "pch_hda_idisp_codec_enable" = "1"
 
 	# DPTF enable
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	device domain 0 on
 		device ref igpu on end

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -71,7 +71,7 @@ chip soc/intel/tigerlake
 	register "s0ix_enable" = "true"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Add PL1 and PL2 values
 	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -78,7 +78,7 @@ chip soc/intel/tigerlake
 	register "s0ix_enable" = "true"
 
 	# Enable DPTF
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	# Add PL1 and PL2 values
 	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{

src/mainboard/kontron/mal10/variants/mal10/devicetree.cb

@@ -3,7 +3,7 @@
 chip soc/intel/apollolake
 
 	register "enable_vtd" = "1"
-	register "dptf_enable" = "1"
+	register "dptf_enable" = "true"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge

src/mainboard/libretrend/lt1000/devicetree.cb

@@ -24,7 +24,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Disable DPTF
-	register "dptf_enable" = "0"
+	register "dptf_enable" = "false"
 
 	# FSP Configuration
 	register "DspEnable" = "1"

src/mainboard/protectli/vault_kbl/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/skylake
 	register "eist_enable" = "true"
 
 	# Disable DPTF
-	register "dptf_enable" = "0"
+	register "dptf_enable" = "false"
 
 	register "tcc_offset" = "5" # TCC of 95C
 

src/mainboard/purism/librem_skl/devicetree.cb

@@ -35,7 +35,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Disable DPTF
-	register "dptf_enable" = "0"
+	register "dptf_enable" = "false"
 
 	# FSP Configuration
 	register "DspEnable" = "0"

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -16,7 +16,7 @@ chip soc/intel/skylake
 	register "gpe0_dw2" = "GPP_E"
 
 	# Disable DPTF
-	register "dptf_enable" = "0"
+	register "dptf_enable" = "false"
 
 	# FSP Configuration
 	register "DspEnable" = "0"