soc/intel/meteorlake: Move CNVi control out of chipset.cb

Not every board will use CNVi, so move this out of the chipset.cb
and into devicetree.

Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2025-01-21 15:41:02 +00:00
commit e15c97c56c
5 changed files with 7 additions and 3 deletions

View file

@ -1,4 +1,6 @@
chip soc/intel/meteorlake
# Enable CNVi WiFi
register "cnvi_wifi_core" = "true"
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_D"

View file

@ -1,4 +1,6 @@
chip soc/intel/meteorlake
# Enable CNVi WiFi
register "cnvi_wifi_core" = "true"
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_B"

View file

@ -9,6 +9,8 @@ fw_config
end
chip soc/intel/meteorlake
# Enable CNVi WiFi
register "cnvi_wifi_core" = "true"
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_B"

View file

@ -34,6 +34,7 @@ chip soc/intel/meteorlake
device ref ioe_shared_sram on end
device ref pmc_shared_sram on end
device ref cnvi_wifi on
register "cnvi_wifi_core" = "true"
register "cnvi_bt_core" = "true"
register "cnvi_bt_audio_offload" = "true"
chip drivers/wifi/generic

View file

@ -29,9 +29,6 @@ chip soc/intel/meteorlake
# Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
register "tcc_offset" = "20"
# Enable CNVi WiFi
register "cnvi_wifi_core" = "true"
device domain 0 on
device pci 00.0 alias system_agent on end
device pci 01.0 alias pcie_rp12 off end