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soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param

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According to Intel's recommendation for Time Coordinated Computing (TCC)
the FSP-S parameter PchLegacyIoLowLatency should be set to 'Enabled'
in order to promote low latencies on the PCH.
With the previous setting 'Disabled' low latencies on the PCH for
I/O operations are not enhanced.

Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86068
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johannes Hahn 2025-01-07 17:29:34 +01:00 • committed by Matt DeVillier
commit 20bee312f4
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/elkhartlake/fsp_params.c
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@ -329,7 +329,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PsfTccEnable = 1;
params->PmcLpmS0ixSubStateEnableMask = 0;
params->PchDmiAspmCtrl = 0;
params->PchLegacyIoLowLatency = 0;
params->PchLegacyIoLowLatency = 1;
params->EnableItbm = 0;
params->D3ColdEnable = 0;
params->PmcOsIdleEnable = 0;