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soc/intel/pantherlake: Add platform debug option for FSP

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Previously, DCI was enabled unconditionally, which could interfere with
the USB data path when connected behind a powered hub and/or servo v4.1
debug connector.

This patch sets DciEn parameter based on the selected platform debug
option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is
set to 0.

BUG=b:384453901
TEST=Able to boot google/fatcat.

Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This commit is contained in:
Subrata Banik 2025-01-22 16:26:22 +05:30
commit 7c1a9ba9b4
2 changed files with 28 additions and 1 deletions
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17
src/soc/intel/pantherlake/chip.h
View file

@ -121,6 +121,23 @@ enum lpm_state_mask {
| LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
};
/* Platform Debug Option using HW interface
*
* 0: Disabled,
* 2: Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix,
* 4: Enabled Trace ready: TraceHub is enabled and allowed S0ix,
* 6: Enabled Trace power off: TraceHub is powergated, provide setting close to functional
* low power state,
* 7: User needs to configure Advanced Debug Settings manually. (only applicable for devices
* with BIOS Setup Menu option present.
*/
enum platform_hw_debug_option {
HW_DEBUG_DISABLE = 0,
HW_DEBUG_TRACEHUB_ACTIVE = BIT(1),
HW_DEBUG_TRACEHUB_READY = BIT(2),
HW_DEBUG_TRACEHUB_POWEROFF = BIT(2) | BIT(1),
};
/*
* As per definition from FSP header:
* - [0] for IA

12
src/soc/intel/pantherlake/romstage/fsp_params.c
View file

@ -253,7 +253,17 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG);
m_cfg->DciEn = 1;
switch (CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT) {
case HW_DEBUG_TRACEHUB_ACTIVE:
case HW_DEBUG_TRACEHUB_READY:
case HW_DEBUG_TRACEHUB_POWEROFF:
m_cfg->DciEn = 1;
break;
case HW_DEBUG_DISABLE:
m_cfg->DciEn = 0;
break;
}
}
static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg,