mb/google/brya: Create pujjoniru variant
Create the pujjoniru variant of the nissa reference board by copying the template files to a new directory named for the variant. And based on schematics PujjoNiru_C5_CHROME_TWL_SCH_MB_V1_1225A.pdf update devicetree settings. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=b:386221423 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJONIRU Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85844 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Qinghong Zeng
Subrata Banik
parent
eccbf5186d
commit
ffc74367e0
11 changed files with 898 additions and 0 deletions
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@ -455,6 +455,16 @@ config BOARD_GOOGLE_PUJJOGATWIN
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_PUJJONIRU
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select BOARD_ROMSIZE_KB_16384
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_GENERIC_BAYHUB_LV2
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GFX_GENERIC
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select DRIVERS_AUDIO_SOF
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_QUANDISO
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select CHROMEOS_WIFI_SAR if CHROMEOS
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@ -770,6 +780,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x0 if BOARD_GOOGLE_PIRRHA
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default 0x1 if BOARD_GOOGLE_PRIMUS
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default 0x0 if BOARD_GOOGLE_PUJJO
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default 0x0 if BOARD_GOOGLE_PUJJONIRU
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default 0x0 if BOARD_GOOGLE_QUANDISO
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default 0x0 if BOARD_GOOGLE_QUANDISO2
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default 0x1 if BOARD_GOOGLE_REDRIX
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@ -850,6 +861,7 @@ config TPM_TIS_ACPI_INTERRUPT
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default 13 if BOARD_GOOGLE_PIRRHA
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default 13 if BOARD_GOOGLE_PRIMUS
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default 13 if BOARD_GOOGLE_PUJJO
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default 13 if BOARD_GOOGLE_PUJJONIRU
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default 13 if BOARD_GOOGLE_QUANDISO
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default 13 if BOARD_GOOGLE_QUANDISO2
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default 13 if BOARD_GOOGLE_REDRIX
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@ -935,6 +947,7 @@ config MAINBOARD_PART_NUMBER
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default "Pirrha" if BOARD_GOOGLE_PIRRHA
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default "Primus" if BOARD_GOOGLE_PRIMUS
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default "Pujjo" if BOARD_GOOGLE_PUJJO
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default "Pujjoniru" if BOARD_GOOGLE_PUJJONIRU
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default "Quandiso" if BOARD_GOOGLE_QUANDISO
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default "Quandiso2" if BOARD_GOOGLE_QUANDISO2
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default "Redrix" if BOARD_GOOGLE_REDRIX
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@ -1010,6 +1023,7 @@ config VARIANT_DIR
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default "pirrha" if BOARD_GOOGLE_PIRRHA
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default "primus" if BOARD_GOOGLE_PRIMUS
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default "pujjo" if BOARD_GOOGLE_PUJJO
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default "pujjoniru" if BOARD_GOOGLE_PUJJONIRU
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default "quandiso" if BOARD_GOOGLE_QUANDISO
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default "quandiso" if BOARD_GOOGLE_QUANDISO2
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default "redrix" if BOARD_GOOGLE_REDRIX
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@ -119,6 +119,9 @@ config BOARD_GOOGLE_PRIMUS
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config BOARD_GOOGLE_PUJJO
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bool "-> Pujjo"
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config BOARD_GOOGLE_PUJJONIRU
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bool "-> Pujjoniru"
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config BOARD_GOOGLE_QUANDISO
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bool "-> Quandiso"
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9
src/mainboard/google/brya/variants/pujjoniru/Makefile.mk
Normal file
9
src/mainboard/google/brya/variants/pujjoniru/Makefile.mk
Normal file
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@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += variant.c
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203
src/mainboard/google/brya/variants/pujjoniru/gpio.c
Normal file
203
src/mainboard/google/brya/variants/pujjoniru/gpio.c
Normal file
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@ -0,0 +1,203 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A7 : NC ==> SLP_S0_GATE_R */
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PAD_CFG_GPI(GPP_A7, NONE, DEEP),
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/* A8 : GPP_A8 ==> NC */
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PAD_NC_LOCK(GPP_A8, NONE, LOCK_CONFIG),
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/* A11 : GPP_A11 ==> EN_SPK_PA */
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PAD_CFG_GPO(GPP_A11, 0, DEEP),
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/* A18 : NC ==> HDMI_HPD_SRC*/
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
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/* A21 : GPP_A21 ==> NC */
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PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
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/* A22 : GPP_A22 ==> NC */
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PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
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/* B3 : NC ==> MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_B3, NONE, DEEP),
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/* B5 : I2C2_SDA ==> NA */
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PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
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/* B6 : I2C2_SCL ==> NA */
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PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
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/* B11 : NC ==> EN_PP3300_WLAN_X*/
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PAD_CFG_GPO(GPP_B11, 1, DEEP),
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/* D11 : EN_PP1800_WCAM_X ==> NC */
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PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
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/* B4 : SSD_PERST_L ==> NC */
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PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
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/* D0 : NC ==> PCH_FP_BOOT0 */
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PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
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/* D2 : NC ==> EN_FP_PWR */
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PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG),
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/* D3 : ISH_GP3 ==> SD_WAKE_N */
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PAD_CFG_GPI_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D6 : WWAN_PWR_ENABLE ==> NC */
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PAD_NC_LOCK(GPP_D6, NONE, LOCK_CONFIG),
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/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* D13 : EN_PP1800_WCAM_X ==> NA */
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PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
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/* D15 : EN_PP2800_WCAM_X ==> NA */
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PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
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/* D16 : EN_PP1800_PP1200_WCAM_X ==> NA */
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PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
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/* D17 : NC ==> UART_AP_RX_FP_TX */
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PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* D18 : NC ==> UART_AP_TX_FP_RX */
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PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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/* E4 : NA ==> NC */
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PAD_NC_LOCK(GPP_E4, NONE, LOCK_CONFIG),
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/* E5 : NA ==> NC */
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PAD_NC_LOCK(GPP_E5, NONE, LOCK_CONFIG),
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/* E7 : NC ==> FP_RST_ODL */
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PAD_CFG_GPO_LOCK(GPP_E7, 0, LOCK_CONFIG),
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/* E10 : NC ==> GSPI1_SOC_TCHSCR_CS_L */
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PAD_CFG_NF_LOCK(GPP_E10, NONE, NF7, LOCK_CONFIG),
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/* E11 : NC ==> GSPI1_SOC_TCHSCR_CLK */
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PAD_CFG_NF_LOCK(GPP_E11, NONE, NF7, LOCK_CONFIG),
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/* E12 : NC ==> GSPI1_SOC_MISO_TCHSCR */
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PAD_CFG_NF_LOCK(GPP_E12, NONE, NF7, LOCK_CONFIG),
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/* E13 : NC ==> GSPI1_SOC_MOSI_TCHSCR */
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PAD_CFG_NF_LOCK(GPP_E13, NONE, NF7, LOCK_CONFIG),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
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/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
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PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
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/* F11 : NC ==> GSPI_PCH_CLK_FPMCU */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
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/* F12 : WWAN_RST_L ==> GSPI_PCH_DO_FPMCU_DI_R */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
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/* F13 : SOC_PEN_DETECT_R_ODL ==> GSPI_PCH_DI_FPMCU_DO */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
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/* F15 : SOC_PEN_DETECT_ODL ==> FPMCU_INT_L */
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PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
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/* F16 : NC ==> GSPI_PCH_CS_FPMCU_R_L */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
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/* F23 : V1P05_CTRL ==> NC*/
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PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
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/* H12 : UART0_RTS# ==> SD_PERST_L*/
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PAD_CFG_GPO_LOCK(GPP_H12, 1, LOCK_CONFIG),
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/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
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PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
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/* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
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PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
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/* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
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/* H22 : WCAM_MCLK_R ==> NA */
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PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG),
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/* H23 : WWAN_SAR_DETECT_ODL ==> NA */
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PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
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/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
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PAD_CFG_GPO(GPP_H20, 1, DEEP),
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/* I7 : EMMC_CMD ==> NC */
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PAD_NC_LOCK(GPP_I7, NONE, LOCK_CONFIG),
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/* I8 : EMMC_D0 ==> NC*/
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PAD_NC_LOCK(GPP_I8, NONE, LOCK_CONFIG),
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/* I9 : EMMC_D1 ==> NC */
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PAD_NC_LOCK(GPP_I9, NONE, LOCK_CONFIG),
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/* I10 : EMMC_D2 ==> NC */
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PAD_NC_LOCK(GPP_I10, NONE, LOCK_CONFIG),
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/* I11 : EMMC_D3 ==> NC */
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PAD_NC_LOCK(GPP_I11, NONE, LOCK_CONFIG),
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/* I12 : EMMC_D4 ==> NC */
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PAD_NC_LOCK(GPP_I12, NONE, LOCK_CONFIG),
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/* I13 : EMMC_D5 ==> NC */
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PAD_NC_LOCK(GPP_I13, NONE, LOCK_CONFIG),
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/* I14 : EMMC_D6 ==> NC */
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PAD_NC_LOCK(GPP_I14, NONE, LOCK_CONFIG),
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/* I15 : EMMC_D7 ==> NC */
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PAD_NC_LOCK(GPP_I15, NONE, LOCK_CONFIG),
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/* I16 : EMMC_RCLK ==> NC */
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PAD_NC_LOCK(GPP_I16, NONE, LOCK_CONFIG),
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/* I17 : EMMC_CLK ==> NC */
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PAD_NC_LOCK(GPP_I17, NONE, LOCK_CONFIG),
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/* I18 : EMMC_RST_L ==> NC */
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PAD_NC_LOCK(GPP_I18, NONE, LOCK_CONFIG),
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/* R6 : DMIC_WCAM_CLK_R ==> NC */
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PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
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/* R7 : DMIC_WCAM_DATA ==> NC */
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PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
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/* C7 : SML1DATA ==> TCHSCR_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
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/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
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/* BT_I2S_BCLK */
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PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
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/* BT_I2S_SYNC */
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PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
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/* BT_I2S_SDO */
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PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
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/* BT_I2S_SDI */
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PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
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/* SSP2_SCLK */
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PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
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/* SSP2_SFRM */
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PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
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/* SSP_TXD */
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PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
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/* SSP_RXD */
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PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* E17 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E17, NONE, DEEP),
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/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
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PAD_CFG_GPO(GPP_H20, 0, DEEP),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_C1, 0, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __VARIANT_EC_H__
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#define __VARIANT_EC_H__
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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#endif
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@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoniru/memory src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt
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SPD_SOURCES =
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SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT
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SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E
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SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56CK8BX146
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SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
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@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoniru/memory src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt
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DRAM Part Name ID to assign
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K3KL6L60GM-MGCT 0 (0000)
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H9JCNNNBK3MLYR-N6E 1 (0001)
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H58G56CK8BX146 2 (0010)
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MT62F1G32D2DS-026 WT:B 3 (0011)
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K3KL8L80CM-MGCT 3 (0011)
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@ -0,0 +1,16 @@
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# This is a CSV file containing a list of memory parts used by this variant.
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# One part per line with an optional fixed ID in column 2.
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# Only include a fixed ID if it is required for legacy reasons!
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# Generated IDs are dependent on the order of parts in this file,
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# so new parts must always be added at the end of the file!
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#
|
||||
# Generate an updated Makefile.inc and dram_id.generated.txt by running the
|
||||
# part_id_gen tool from util/spd_tools.
|
||||
# See util/spd_tools/README.md for more details and instructions.
|
||||
|
||||
# Part Name
|
||||
K3KL6L60GM-MGCT
|
||||
H9JCNNNBK3MLYR-N6E
|
||||
H58G56CK8BX146
|
||||
MT62F1G32D2DS-026 WT:B
|
||||
K3KL8L80CM-MGCT
|
||||
589
src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
Normal file
589
src/mainboard/google/brya/variants/pujjoniru/overridetree.cb
Normal file
|
|
@ -0,0 +1,589 @@
|
|||
fw_config
|
||||
field WIFI 3 4
|
||||
option WIFI_CNVI_WIFI6E 0
|
||||
option WIFI_PCIE_WIFI7 1
|
||||
option WIFI_UNKNOWN 2
|
||||
end
|
||||
field THERMAL 9 9
|
||||
option THERMAL_6W 0
|
||||
option THERMAL_15W 1
|
||||
end
|
||||
field FP 10 10
|
||||
option FP_ABSENT 0
|
||||
option FP_PRESENT 1
|
||||
end
|
||||
end
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "sagv" = "SaGv_Enabled"
|
||||
|
||||
# SOC Aux orientation override:
|
||||
# This is a bitfield that corresponds to up to 4 TCSS ports.
|
||||
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
|
||||
# TcssAuxOri = 0100b
|
||||
# Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
|
||||
# Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
|
||||
# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
|
||||
# motherboard to USBC connector
|
||||
register "tcss_aux_ori" = "5"
|
||||
|
||||
register "typec_aux_bias_pads[0]" = "{
|
||||
.pad_auxp_dc = GPP_E22,
|
||||
.pad_auxn_dc = GPP_E23
|
||||
}"
|
||||
|
||||
register "typec_aux_bias_pads[1]" = "{
|
||||
.pad_auxp_dc = GPP_A21,
|
||||
.pad_auxn_dc = GPP_A22
|
||||
}"
|
||||
|
||||
# FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn
|
||||
# bypass rails implemented.
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 0,
|
||||
}"
|
||||
|
||||
# Enable the Cnvi BT Audio Offload
|
||||
register "cnvi_bt_audio_offload" = "1"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------+------------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------+------------------------------+
|
||||
#| gspi0 | Touchscreen |
|
||||
#| gspi1 | Fingerprint MCU |
|
||||
#| I2C0 | TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C3 | Audio |
|
||||
#| I2C5 | Trackpad |
|
||||
#+-------------+------------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.scl_lcnt = 55,
|
||||
.scl_hcnt = 30,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 157,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 152,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
# Power limit config
|
||||
register "power_limits_config[ADL_N_041_6W_CORE]" = "{
|
||||
.tdp_pl1_override = 15,
|
||||
.tdp_pl2_override = 25,
|
||||
.tdp_pl4 = 78,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""CPU_VR""
|
||||
register "options.tsr[1].desc" = ""CPU""
|
||||
register "options.tsr[2].desc" = ""Ambient""
|
||||
register "options.tsr[3].desc" = ""Charger""
|
||||
|
||||
# TODO: below values are initial reference values only
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 85, 6000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000),
|
||||
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000),
|
||||
[4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 6000,
|
||||
.max_power = 6000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 25000,
|
||||
.max_power = 25000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 3000 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 4734, 220, 1640, },
|
||||
[1] = { 80, 4443, 180, 1310, },
|
||||
[2] = { 70, 4108, 145, 1030, },
|
||||
[3] = { 60, 3752, 115, 765, },
|
||||
[4] = { 50, 3352, 90, 545, },
|
||||
[5] = { 40, 2897, 55, 365, },
|
||||
[6] = { 30, 2363, 30, 220, },
|
||||
[7] = { 20, 1752, 15, 120, },
|
||||
[8] = { 10, 918, 10, 60, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "1"
|
||||
register "options.fan.step_size" = "2"
|
||||
device generic 0 on
|
||||
probe THERMAL THERMAL_6W
|
||||
end
|
||||
end
|
||||
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""CPU_VR""
|
||||
register "options.tsr[1].desc" = ""CPU""
|
||||
register "options.tsr[2].desc" = ""Ambient""
|
||||
register "options.tsr[3].desc" = ""Charger""
|
||||
|
||||
# TODO: below values are initial reference values only
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_TEMP_SENSOR_0,
|
||||
.thresholds = {
|
||||
TEMP_PCT(85, 90),
|
||||
TEMP_PCT(54, 64),
|
||||
TEMP_PCT(52, 52),
|
||||
TEMP_PCT(50, 44),
|
||||
TEMP_PCT(48, 38),
|
||||
TEMP_PCT(45, 34),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_1,
|
||||
.thresholds = {
|
||||
TEMP_PCT(75, 90),
|
||||
TEMP_PCT(70, 80),
|
||||
TEMP_PCT(65, 70),
|
||||
TEMP_PCT(60, 60),
|
||||
TEMP_PCT(55, 50),
|
||||
TEMP_PCT(50, 40),
|
||||
}
|
||||
},
|
||||
[2] = {
|
||||
.target = DPTF_TEMP_SENSOR_2,
|
||||
.thresholds = {
|
||||
TEMP_PCT(90, 90),
|
||||
TEMP_PCT(85, 80),
|
||||
TEMP_PCT(75, 70),
|
||||
TEMP_PCT(70, 50),
|
||||
}
|
||||
},
|
||||
[3] = {
|
||||
.target = DPTF_TEMP_SENSOR_3,
|
||||
.thresholds = {
|
||||
TEMP_PCT(80, 90),
|
||||
TEMP_PCT(75, 80),
|
||||
TEMP_PCT(70, 70),
|
||||
TEMP_PCT(65, 50),
|
||||
}
|
||||
}
|
||||
}"
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 85, 6000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000),
|
||||
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 6000),
|
||||
[4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 15000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 35000,
|
||||
.max_power = 35000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 3000 },
|
||||
[1] = { 24, 2000 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 100, 4000, 220, 1640, },
|
||||
[1] = { 90, 3700, 220, 1640, },
|
||||
[2] = { 80, 3500, 180, 1310, },
|
||||
[3] = { 70, 3300, 145, 1030, },
|
||||
[4] = { 60, 3100, 115, 765, },
|
||||
[5] = { 50, 2800, 90, 545, },
|
||||
[6] = { 40, 2500, 55, 365, },
|
||||
[7] = { 30, 2100, 30, 220, },
|
||||
[8] = { 20, 1500, 15, 120, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "1"
|
||||
register "options.fan.step_size" = "2"
|
||||
device generic 1 on
|
||||
probe THERMAL THERMAL_15W
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref ish on
|
||||
chip drivers/intel/ish
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe STORAGE STORAGE_UFS
|
||||
end
|
||||
device ref ufs on
|
||||
probe STORAGE STORAGE_UFS
|
||||
end
|
||||
device ref igpu on
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "4"
|
||||
# DDIA for eDP
|
||||
register "device[0].name" = ""LCD0""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].type" = "panel"
|
||||
# DDIB for HDMI
|
||||
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
|
||||
register "device[1].name" = ""DD01""
|
||||
# TCP0 (DP-1) for port C0
|
||||
register "device[2].name" = ""DD02""
|
||||
register "device[2].use_pld" = "true"
|
||||
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
|
||||
# TCP1 (DP-2) for port C1
|
||||
register "device[3].name" = ""DD03""
|
||||
register "device[3].use_pld" = "true"
|
||||
register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c3 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
chip drivers/generic/alc1015
|
||||
register "hid" = ""RTL1019""
|
||||
register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "wake" = "GPE0_DW2_14"
|
||||
register "detect" = "1"
|
||||
device i2c 0x15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FTCS0038""
|
||||
register "generic.cid" = ""PNP0C50""
|
||||
register "generic.desc" = ""Focal Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_14"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 0x38 on end
|
||||
end
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI WIFI_CNVI_WIFI6E
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
device ref pcie_rp4 on
|
||||
# PCIe 4 WLAN
|
||||
register "pch_pcie_rp[PCH_RP(4)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_DW1_03"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
|
||||
register "srcclk_pin" = "2"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI WIFI_PCIE_WIFI7
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port2 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port2 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
|
||||
register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
|
||||
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 LTE""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 UFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""PCIe Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port8 on
|
||||
probe WIFI WIFI_PCIE_WIFI7
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""CNVi Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on
|
||||
probe WIFI WIFI_CNVI_WIFI6E
|
||||
probe WIFI WIFI_UNKNOWN
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WLAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp7 on
|
||||
# Enable SD Card PCIE 7 using clk 3
|
||||
register "pch_pcie_rp[PCH_RP(7)]" = "{
|
||||
.clk_src = 3,
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
|
||||
register "srcclk_pin" = "3"
|
||||
device generic 0 on end
|
||||
end
|
||||
end #PCIE7 SD card
|
||||
device ref pcie_rp9 off end
|
||||
device ref hda on
|
||||
chip drivers/sof
|
||||
register "spkr_tplg" = "rt1019"
|
||||
register "jack_tplg" = "rt5682"
|
||||
register "mic_tplg" = "_2ch_pdm0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref gspi0 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""GTP0""
|
||||
register "hid" = ""GXTS7986""
|
||||
register "uid" = "0x3"
|
||||
register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_C7_IRQ)"
|
||||
register "speed" = "9 * MHz"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""goodix,hid-report-addr""
|
||||
register "property_list[0].integer" = "0x22c8c"
|
||||
device spi 0 on end
|
||||
end # touchscreen
|
||||
end
|
||||
device ref gspi1 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "uid" = "1"
|
||||
register "compat_string" = ""google,cros-ec-spi""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
register "has_power_resource" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
|
||||
register "enable_delay_ms" = "3"
|
||||
device spi 0 on
|
||||
probe FP FP_PRESENT
|
||||
end
|
||||
end # FPMCU
|
||||
end
|
||||
end
|
||||
end
|
||||
27
src/mainboard/google/brya/variants/pujjoniru/variant.c
Normal file
27
src/mainboard/google/brya/variants/pujjoniru/variant.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
#include <soc/gpio_soc_defs.h>
|
||||
#include <intelblocks/graphics.h>
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
|
||||
}
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E))
|
||||
|| fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) {
|
||||
printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
|
||||
config->cnvi_bt_core = true;
|
||||
config->cnvi_bt_audio_offload = true;
|
||||
} else {
|
||||
printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
|
||||
config->cnvi_bt_core = false;
|
||||
config->cnvi_bt_audio_offload = false;
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue