soc/mediatek/commmon: Set mcupm mcufw_reserved region to non-cacheable

Set mcufw_reserved region to non-cacheable and remove cache operation in
dvfs.c.

TEST=Build pass, boot ok.
Check MMU List by CVD (Codeviser):
0x00113000--0x00123FFF  = I:non-cacheable O:non-cacheable
BUG=b:390334489

Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86159
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>

src/soc/mediatek/common/include/soc/symbols.h

@@ -9,6 +9,6 @@ DECLARE_REGION(dram_dma)
 DECLARE_REGION(resv_mem_optee)
 DECLARE_REGION(resv_mem_gpu)
 DECLARE_REGION(resv_mem_gpueb)
-DECLARE_REGION(mcufw_reserved)
+DECLARE_OPTIONAL_REGION(mcufw_reserved)
 
 #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */

src/soc/mediatek/common/mmu_operations.c

@@ -4,6 +4,7 @@
 #include <symbols.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
+#include <soc/symbols.h>
 
 __weak void mtk_soc_after_dram(void) { /* do nothing */ }
 
@@ -35,6 +36,11 @@ void mtk_mmu_init(void)
 	mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent),
 			 SECURE_UNCACHED_MEM);
 
+	/* Set mcufw_reserved to non-cacheable */
+	if (REGION_SIZE(mcufw_reserved) != 0)
+		mmu_config_range(_mcufw_reserved, REGION_SIZE(mcufw_reserved),
+				 SECURE_UNCACHED_MEM);
+
 	mmu_enable();
 }
 

src/soc/mediatek/mt8196/dvfs.c

@@ -12,6 +12,4 @@ void dvfs_init(void)
 
 	write32p(CSRAM_BASE + 0x8, 0x55AA55AA);
 	write32p(CSRAM_BASE + 0xC, val);
-
-	dcache_clean_invalidate_by_mva((void *)CSRAM_BASE, CACHE_LINE);
 }