Enable clocks for Type-C ports C0 and C1.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
BUG=b:448107633
TEST = Verified that all the clocks added are ON during usb init.
BIT31[CLK OFF] of CBCR register of respective clock indicates
clock status.
Clock Configuration Status:
Clock Name State Register Value
----------------------------------------------------------------
gcc_usb30_mp_master_clk ON 0x00117018 0x00000001
gcc_usb30_mp_sleep_clk ON 0x00117024 0x00000001
gcc_usb30_mp_mock_utmi_clk ON 0x00117028 0x00000001
gcc_usb3_mp_phy_aux_clk ON 0x00117288 0x00000001
gcc_usb3_mp_phy_com_aux_clk ON 0x0011728C 0x00000001
gcc_usb3_mp_phy_pipe_0_clk ON 0x00117290 0x00000001
gcc_usb3_mp_phy_pipe_1_clk ON 0x00117298 0x00000001
gcc_cfg_noc_usb3_mp_axi_clk ON 0x001173CC 0x00000001
gcc_aggre_usb3_mp_axi_clk ON 0x001173D0 0x00000001
gcc_sys_noc_usb_axi_clk ON 0x0012D014 0x00000001
gcc_cfg_noc_usb_anoc_north_ahb_clk ON 0x0012D028 0x00000000
gcc_cfg_noc_usb_anoc_south_ahb_clk ON 0x0012D02C 0x00000000
gcc_aggre_usb_noc_axi_clk ON 0x0012D034 0x00000001
gcc_cfg_noc_usb_anoc_ahb_clk ON 0x0012D024 0x00000000
gcc_usb30_prim_master_clk ON 0x00139018 0x00000001
gcc_usb30_prim_sleep_clk ON 0x00139024 0x00000001
gcc_usb30_prim_mock_utmi_clk ON 0x00139028 0x00000001
gcc_usb3_prim_phy_com_aux_clk ON 0x00139064 0x00000001
gcc_usb3_prim_phy_pipe_clk ON 0x00139068 0x00000001
gcc_cfg_noc_usb3_prim_axi_clk ON 0x0013908C 0x00000001
gcc_aggre_usb3_prim_axi_clk ON 0x00139090 0x00000001
gcc_cfg_noc_usb3_sec_axi_clk ON 0x001A108C 0x00000001
gcc_aggre_usb3_sec_axi_clk ON 0x001A1090 0x00000001
gcc_usb30_sec_master_clk ON 0x001A1018 0x00000001
gcc_usb30_sec_sleep_clk ON 0x001A1024 0x00000001
gcc_usb30_sec_mock_utmi_clk ON 0x001A1028 0x00000001
gcc_usb3_sec_phy_aux_clk ON 0x001A1060 0x00000001
gcc_usb3_sec_phy_com_aux_clk ON 0x001A1064 0x00000001
gcc_usb3_sec_phy_pipe_clk ON 0x001A1068 0x00000001
Change-Id: I86cd84f515a22a080fe39687c8b7b8c01cb9c001
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89350
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Align DDR and IMEM address definitions with memory layout
specifications. Modify CBMEM top address accordingly.
Changes include:
- Declaring new memory regions in symbols_common.h.
- Defining base addresses and sizes for these regions in memlayout.ld.
- Marking these regions as reserved in soc_read_resources() to
prevent overwrites by coreboot.
- Modifying CBMEM top address.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch downgrades the message severity from BIOS_ERR to
BIOS_WARNING when mrc_cache_load_current() returns an invalid size
(typically during the first boot or after firmware update).
The failure to load previously saved MRC training data from flash is
often non-fatal, as the system can typically proceed to perform a full
memory training run. Therefore, a warning is more appropriate.
The message is also updated to provide crucial diagnostic information,
including the actual and expected data sizes, which aids in debugging
cache corruption or version mismatch issues.
w/o this patch
```
[ERROR] Unable to load previous training data.
```
w/ this patch
```
[WARN ] qclib: Invalid MRC data in flash (size: 0xffffffffffffffff, expected: 0x10000)
```
Change-Id: I810c868adf923e4527abe06a857b15950aa8f17a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Select the newly introduced `HAVE_CBFS_FILE_OPTION_BACKEND` capability
for the Qualcomm x1p42100 SoC family.
This SoC is used in ChromeOS devices that rely on the CBFS file backend
to store and retrieve runtime configuration options (like the QCLib
configuration data). Selecting this capability ensures the correct
option backend is chosen in the Kconfig `Option backend to use` choice.
TEST=Build and boot a board using the x1p42100 SoC (e.g., bluey).
Confirm the `CONFIG_USE_CBFS_FILE_OPTION_BACKEND` option is enabled
in the build.
Change-Id: Ie0dee155a504da215669a79d7100cdbaf97d5261
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce a new static function, `qclib_debug_log_level`, that
checks a runtime-configurable option, "qclib_debug_level", to
control whether QCLib enables serial logging.
This allows for dynamic control of QCLib's verbose output via a
coreboot option instead of relying solely on the static
`CONFIG(CONSOLE_SERIAL)` Kconfig option. This is necessary because
while the serial console might be enabled for general coreboot
logging, the user may want to suppress the often extensive and
low-level output from QCLib to keep the console clean during normal
operations.
The check for enabling QCLib's serial output is updated from
`if (CONFIG(CONSOLE_SERIAL))` to
`if (CONFIG(CONSOLE_SERIAL) && qclib_debug_log_level())`
The option value is read using
`get_uint_option("qclib_debug_level", 1)`, meaning the default
behavior is to enable QCLib logging if `CONSOLE_SERIAL` is set,
maintaining backward compatibility unless the option is explicitly
set to 0 at runtime.
BUG=b:445211186
TEST=Build and boot a Qualcomm platform with CONFIG_CONSOLE_SERIAL
enabled. Confirmed QCLib logs are present by default.
Set option "qclib_debug_level" to 0 via CBFS option and confirmed
QCLib logs are suppressed while coreboot serial output remains
active.
Change-Id: I2c7326fae889508f09e1eb5e3863456cf54f5c29
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for HS-PHY/SS-PHY and DWC3 USB controllers
for USB Type A Host support.
TEST = Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.
Change-Id: Ife08801062da5a8f87491b020b3828c246aadea8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for USB controller, PHY and NOC clocks.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Verify the boot process on the X1P42100 by creating an
image.serial.bin. After booting, confirm that the USB clocks are
on by inspecting the Clock Branch Control Register (CBCR) for
each clock. The status is indicated by BIT31, where a low value
means the clock is on.
Change-Id: Ic78e75c2c9963311530172d802aabb03f540060c
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implements clock-based reset control via CLK_CTL_ARES_SHFT bit
in CBC, enabling reset of cores receiving CBC-generated clocks.
This is required for proper initialization of clocks needed for
subsystems like USB Type-A.
TEST: Verified on x1p42100 CRD by asserting CLK_ARES through CBC
register writes during USB Type-A enablement. Confirmed USB
enumeration and reset functionality serial console.
Change-Id: If878994eaa24a21061470f962a4883f29be5476f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
:wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89102
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the DRAM memory reservation range for TF-A
to align with the latest Bluey memory layout specifications.
TEST=Verified boot up on google/bluey.
Change-Id: Ifb67e591d0f3d28cd6b0856198b29af49c2aab4c
Signed-off-by: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The SPMI (System Power Management Interface) driver is necessary
for power management functionalities on the Qualcomm x1p42100 SoC.
This commit adds spmi.c to the ramstage-y list in the Makefile.mk,
ensuring that the SPMI driver is compiled and available during the
ramstage of the coreboot execution.
TEST=Able to build and boot google/quenbi.
Change-Id: Iba0a423e4a25d7ec9c55e24a1463a4fd4c53cc4f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The memlayout.ld for X1P42100 was copied from a previous SoC and
lacked clear documentation about the platform's specific memory
organization.
This commit adds a detailed ASCII art diagram that provides a visual
representation of the complete memory map. The diagram clarifies the
locations of all major regions, such as AOPSRAM, SSRAM, BSRAM, SHRM,
and the various DRAM segments, which greatly improves the clarity and
maintainability of the linker script.
TEST=Builds successfully for x1p42100.
Change-Id: Ia1714f8da25a22a13f5960d056df33463dd99f31
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88783
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPR image is required by Qclib for PMIC initialization. This patch adds
support to pack and load the CPR binary, reserves memory for CPR
settings in the memory layout and adds CPR entry in if_table which
is passed to Qclib.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPR load log from coreboot.
```
[INFO ] CBFS: Found 'fallback/cpr' @0xa3900 size 0x46d in mcache
@0x1485e340
[INFO ] VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
supported for secdata_kernel v0, return 0
[INFO ] VB2:vb2_digest_init() 1133 bytes, hash algo 2, HW acceleration
forbidden
[INFO ] CBFS: Found 'fallback/shrm_meta' @0xebb80 size 0xb0d in mcache
@0x1485e7c0
```
Change-Id: I58161a1d05222c84e077ada1024db50440e783f1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88870
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPR image is required by Qclib for PMIC initialization. This patch
adds support to declare cpr_settings region and create CBFS prefix
for CPR.
Change-Id: Ia92717715eacaf05d33db040d99cf81d8d288111
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88869
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The alignment for several memory regions in the linker script was
specified using numeric values like `4096` or the hexadecimal `0x1000`.
Replace these values with the more readable `4K` shorthand. This change
improves consistency within the file and has no functional impact on
the generated binary.
TEST=Build and boot google/quenbi.
Change-Id: I28fdf3714d96f5e68a615d1550cf47d975ab5685
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The `SSRAM_START/END`, `BSRAM_START/END`, and `AOPSRAM_START/END`
macros were redefined across multiple Qualcomm SoC `memlayout.ld` files.
To reduce code duplication and improve maintainability, this commit
moves these common macros into the shared `<soc/memlayout.h>` header
part of the Qualcomm common code.
The SoC-specific linker scripts are updated to remove the local
definitions.
TEST=Built for all affected SoCs (qcs405, sc7180, sc7280, x1p42100)
Change-Id: I8638b8e03e1e51f57b7e91a072f3d9cdb4ec6200
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88782
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the common Qualcomm SoC include path to the qcs405 Makefile.
This allows the SoC-specific code to use shared headers located in
`src/soc/qualcomm/common/include`, promoting better code reuse and
organization.
TEST=Build for qcs405 target successfully.
Change-Id: Ie4bc9f3a4fc259adcdc4107c92aab0cb5c8676c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors how the CBMEM top address is determined. Instead
of using a hardcoded value, the CBMEM top address is now starts at
offset `_dram_smem`.
Note: CBMEM region grows from top to bottom hence, starting cbmem_top
at offset `_dram_smem` won't override the SMEM reserved range.
The hardcoded value is problematic as it overrides the SMEM reserved
range and resulted into the boot halt.
The changes include:
- cbmem.c: The cbmem_top_chipset() function is updated to return the
address of the `_dram_smem` linker symbol plus its size.
This refactoring removes a magic number from the code, improving
readability, maintainability, and consistency with how other memory
regions are handled.
BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel w/o
abrupt shutdown.
```
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0xff7ff000 254 entries.
[DEBUG] IMD: root @ 0xff7fec00 62 entries.
```
Change-Id: Idb6a8a47f38d873c6ad4f0d995e77e657cc00ac0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the DRAM memory layout to reserve additional
regions critical for platform functionality and debugging. It
consolidates several CPUCP-related memory areas and adds new
reservations for Ramdump and Shared Memory.
- Ramdump and Shared Memory: New reserved regions, dram_ramdump and
dram_smem, are added to protect memory used for crash dumps and
inter-processor communication.
- CPUCP Optimization: The individual NCC, CPUCP, and CPUCP-DTS regions
are consolidated into a single, contiguous dram_cpucp region from
0x80A00000 to 0x815A0000. This simplifies the memory map and
optimizes resource allocation.
Reserving these regions is crucial to prevent other bootloader stages
or the kernel from overwriting critical firmware data, which could lead
to unexpected behavior or system instability.
BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel.
Change-Id: I80f6d288dd054a34a1e60736c8b14f072559c1ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88779
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the x1p42100 platform to support a dynamic memory
layout for DRAM. This is a crucial step toward supporting different
board variants with varying memory capacities.
The changes involve:
- ramstage build: The mmu.c source file is now included in the ramstage
build, providing the necessary functions to configure the Memory
Management Unit (MMU) for fragmented memory regions.
- Linker Script (memlayout.ld): The dram_space_1 and dram_space_2
regions are statically defined with their maximum possible sizes.
- SoC Initialization (soc.c): The soc_read_resources function is
refactored to use a new helper function, qc_get_soc_dram_space_config,
to retrieve a list of available DRAM regions. It then iterates through
this list to dynamically register each memory region with ram_range.
This replaces the previous static ram_range call with a more flexible
approach that can handle fragmented memory maps. Reserved regions are
also updated to use a dynamic index.
This refactoring allows the system to correctly handle memory maps for
devices with more than 2GB of DRAM, which was a limitation of the
previous static configuration.
TEST=Able to build and boot google/quenbi w/ 16GB of DRAM (using
DDR_SPACE and DDR_SPACE_1 regions).
Change-Id: If94644110272713f77db5a0dd6d23ec0798a15f0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88753
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stating with Qualcomm X1P42100 SoC generation, the DRAM memory map is
not expected to be contiguous (unlike previous generations) therefore,
the memory map could be something like this.
1. Assume hardware design has 4GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (2 GB) : 0x880000000 - 0x900000000
2. Assume hardware design has 16GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (14 GB) : 0x880000000 - 0x400000000
3. Assume hardware design has 64GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (30 GB) : 0x880000000 - 0x1000000000
- DDR_SPACE_2 (32 GB) : 0x8800000000 - 0x9000000000
This commit introduces logic to handle systems with fragmented DRAM
configurations. Previously, the Memory Management Unit (MMU) was
configured assuming a single, contiguous block of DRAM.
This change extends the MMU setup to properly configure multiple,
non-contiguous DRAM regions.
The changes include:
- Declaring dram_space_1 and dram_space_2 as optional regions, allowing
the dynamic allocation for these DRAM ranges based on DRAM capacity of
the platform.
- Introduce `qc_get_soc_dram_space_config` function that takes care of
DRAM based resource splitting as per `_dram`, `_dram_space_1` and
`_dram_space_2` region limit.
- Modifying qc_mmu_dram_config_post_dram_init() to check for these
optional regions and configure them individually. This ensures all
available DRAM is correctly mapped and accessible to the system.
This approach improves flexibility and allows coreboot to support a
wider range of Qualcomm platforms with different memory layouts.
TEST=Able to boot google/quenbi to OS.
Change-Id: If3788f4c77535f9a5e47ad2034ab9a8e0fe85b51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88752
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the qc_mmu_dram_config_post_dram_init function
to remove the ddr_base parameter. The function can now retrieve the
base address of the DRAM from the ddr_region global variable, which
is already available.
TEST=Able to build and boot google/quenbi.
Change-Id: I97159dee6a035ed3e38cbfca1e44b8e671d15fc1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The commit adds new memory regions for the CPUCP (CPU Subsystem Control
Processor) and TZ (TrustZone) components to the x1p42100 SoC. This is
necessary to properly reserve the memory used by these firmware
components during boot.
The changes involve:
- Declaring new memory regions dram_cpucp_dtbs, dram_cpucp, dram_tz,
and dram_tz_rem in the symbols_common.h header.
- Defining the base addresses and sizes for these new regions in
memlayout.ld.
Registering these memory ranges as reserved in the soc_read_resources
function in soc.c so that coreboot does not overwrite them.
TEST=Able to load aop firmware while booting google/quenbi without
boot hang.
Change-Id: I1ecbc1e5ea420b7bdd5518612082ca0e14b35f6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Suggested-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds support to skip DDR training when valid training data
is available in flash.
The exact size of the training data is passed to ensure accurate hash
computation. A hash is computed on the DDR training data using the
specified size and compared with the stored hash in the header. This
requires passing only the exact training data size to ensure correct
validation.
TEST=Create an image.serial.bin and ensure it boots on X1P42100. Verify
that the DDR training is skipped when valid data is available in flash.
w/o this patch: doing RW_MRC_CACHE update in every boot.
```
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG] read SPI 0xc1f290 0xf27c: 5010 us, 12390 KB/s, 99.120 Mbps
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
```
w/ this patch: no need to perform RW_MRC_CACHE update.
```
[DEBUG] FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG] read SPI 0xc10024 0xf268: 5016 us, 12371 KB/s, 98.968 Mbps
```
Change-Id: I1a5ad0766ea77b22e6a8cb97c24a90c24629dfd0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88742
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Updated the memory layout file to include necessary DDR region
reservations for AOP and BL31.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I67b0210dfc563c0a0e8f879b1f41693e1d0e6384
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Introduce a new `SOC_QUALCOMM_HAMOA` Kconfig option and refactor the
Qualcomm SoC build to support Hamoa.
This change prepares the groundwork for Hamoa-based mainboards by:
- Creating a common base: A new `SOC_QUALCOMM_BASE` Kconfig option
is introduced to group configurations shared between Qualcomm SoCs.
- Separating SoC-specific blobs: The build process now dynamically
selects the correct device tree blob (DTB) and display control blob
(DCB) files for Hamoa via a new `DTB_DCB_BLOB_PATH` variable in the
`Makefile.mk`.
- Enabling future mainboards: This allows mainboards built on the Hamoa
SoC to be configured and built within the existing Qualcomm SoC
directory.
BUG=b:437662790
TEST=Able to build and boot google/quenbi.
Change-Id: Ife983495b757fbf06ad96f0ca15fd89bf41c77c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88737
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the Pmic.bin file from the coreboot filesystem
(CBFS) and the Makefile.mk for the Qualcomm x1p42100 SoC.
The PMIC file is no longer used in the boot process. It's safe to
remove it to reduce the size of the final coreboot image and clean
up the build configuration.
TEST=Able to build and boot google/quenbi.
Change-Id: Iac8e4b32677f36959323a5dd3a5c7f88a6359720
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88736
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new Kconfig option, UART_BITBANG_TX_DELAY_MS,
to make the UART TX pin stabilization delay configurable.
A default 5ms (CONFIG_UART_BITBANG_TX_DELAY_MS) delay is added in
uart_init() after the TX pin is set high. This addresses an issue
where the initial character sent by the UART could be corrupted due
to the pin not being stable. The delay ensures the line state is
properly established before data transmission begins.
This was found to resolve early boot console corruption on some boards.
The issue is likely a race condition where the first character starts
transmitting before the GPIO output is fully stabilized.
TEST=Able to build and boot google/zombie w/o any junk characters in
AP firmware log.
w/o this patch:
```
�ɍ���щ�����х�ѥ��b����ٕ��Jrrrjjm UuI5�ፕ�ѥ���������ͥ��х�����jm UuI5���ѥ���ፕ�ѥ��m��jm UuI5����ѕ�ѕፕ�ѥ��m��[DEBUG] NCC Frequency bumped to 1.363(GHz)
```
w/ this patch:
```
[NOTE ] coreboot-25.06-78-gfe786406960e-dirty Fri Aug 01 17:12:22 UTC 2025 aarch64 bootblock starting (log level: 8)...
[DEBUG] ARM64: Exception handlers installed.
[DEBUG] ARM64: Testing exception
[DEBUG] ARM64: Done test exception
[DEBUG] Silver Frequency bumped to 1.5168(GHz)
[DEBUG] L3 Frequency bumped to 1.1904(GHz)
```
Change-Id: I33c9ea65aa42d23acf3b89f977d4985569c144e8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88633
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable bootblock compression on the X1p42100 SoC to decrease boot
time by 10-20 ms.
This change helps to reduce the size of the bootblock, allowing it
to be loaded and decompressed faster, which improves overall boot
performance.
TEST=Able to build and boot google/quenbi.
Change-Id: I81cdbec4a05c8abacae39ff208cc0f7469206161
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88626
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support to pack aop_meta into CBFS and load QcLib DTB,
SHRM metadata, and AOP metadata. It also populates the QcLib interface
table with these information for firmware authentication and execution.
TEST=Verify presence of AOP metadata file in the CBFS and QcLib
interface table content.
Change-Id: I1a74d9ffbfc10023b0e5610d54218909b18efa01
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I9dd9a5340f28326ebabf12489c11e7f73f2c8d2f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88583
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I8a3cb1b21e712e588f641f70c040a2334faf0031
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88543
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support to increase the CPU clock frequency to 1.36(GHz).
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin and ensure it boots on X1P42100 and
CPU runs in 1.36GHz Frequency.
Change-Id: Ie51e032141bdfabf4c96b6891ec9f084561d97ff
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves the shrm_fw_load_reset() API from the SC7280 specific
implementation to the Qualcomm common directory. This change enables
reuse of the API across multiple Qualcomm chipsets.
Change-Id: Ifab870b9aea7396e29fa93c999c29cf11ab0d199
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88545
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor memory layout on x1p42100 to reuse a single reserved region
for all QC image metadata passed from coreboot to QcLib for TME
authentication. Also, reposition the PRERAM_CBMEM_CONSOLE reservation
after the QcLib region to allow for future expansion.
TEST=Successfully booted google/bluey.
Change-Id: I6eea99241c233935c5d99d48093c42bb1424143f
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88485
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to enable PCIE NOC, Controller and PHY clocks.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin, ensure it boots on X1P42100 and
check clock status
Change-Id: I6007a8315343a2d56d51c8472ace831a10146768
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch updates the memory layout for AP Firmware boot on the
Qualcomm x1p42100 SoC. This update is crucial to ensure that all
processors and co-processors can successfully load their
respective blobs during the process of booting to the OS.
TEST=Successfully booted google/blueu.
Change-Id: Ibce385e9d201f0a3c5daf19e8dfe235fa9f695af
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support to enable QUPV3, QSPI and GPLL0 clocks. Modify
XO Source clock frequency value to 19.2KHz. The register
details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin and ensure it boots on X1P42100
Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The register layout for QUP has been updated in QUP v3.2. Update the
structure definition accordingly. Allow SoCs to use the existing version
or the updated version based on QC_COMMON_QUPV3_2.
Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88190
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
