soc/qualcomm/x1p42100: Add Clock support for x1p42100
Add support to enable QUPV3, QSPI and GPLL0 clocks. Modify XO Source clock frequency value to 19.2KHz. The register details are part of HRD-X1P42100-S1 document. https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/ TEST=Create an image.serial.bin and ensure it boots on X1P42100 Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618 Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Swathi Tamilselvan
Subrata Banik
parent
20c2813891
commit
8d8d0f9746
5 changed files with 305 additions and 5 deletions
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@ -22,6 +22,7 @@ config SOC_QUALCOMM_X1P42100
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select PCI
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select QC_COMMON_QUPV3_2
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select NO_ECAM_MMCONF_SUPPORT
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select SDHCI_CONTROLLER
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select SOC_QUALCOMM_COMMON
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@ -6,6 +6,7 @@ decompressor-y += mmu.c
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decompressor-y += ../common/timer.c
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all-y += ../common/timer.c
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all-y += ../common/gpio.c
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all-y += ../common/clock.c
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all-y += clock.c
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all-y += ../common/spi.c
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all-y += ../common/qspi.c
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@ -1,23 +1,185 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <commonlib/helpers.h>
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#include <device/mmio.h>
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#include <soc/clock.h>
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#include <types.h>
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static struct clock_freq_config qspi_core_cfg[] = {
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{
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.hz = SRC_XO_HZ, /* 19.2MHz */
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.src = SRC_XO_19_2MHZ,
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.div = QCOM_CLOCK_DIV(1),
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},
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{
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.hz = 100 * MHz,
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.src = SRC_GPLL0_MAIN_600MHZ,
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.div = QCOM_CLOCK_DIV(6),
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},
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{
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.hz = 150 * MHz,
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.src = SRC_GPLL0_MAIN_600MHZ,
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.div = QCOM_CLOCK_DIV(4),
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},
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{
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.hz = 200 * MHz,
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.src = SRC_GPLL0_MAIN_600MHZ,
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.div = QCOM_CLOCK_DIV(3),
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},
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{
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.hz = 400 * MHz,
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.src = SRC_GPLL0_MAIN_600MHZ,
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.div = QCOM_CLOCK_DIV(1.5),
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},
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};
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static struct clock_freq_config qupv3_wrap_cfg[] = {
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{
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.hz = SRC_XO_HZ, /* 19.2MHz */
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.src = SRC_XO_19_2MHZ,
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.div = QCOM_CLOCK_DIV(1),
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},
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{
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.hz = 32 * MHz,
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.src = SRC_GPLL0_EVEN_300MHZ,
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.div = QCOM_CLOCK_DIV(1),
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.m = 8,
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.n = 75,
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.d_2 = 75,
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},
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{
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.hz = 48 * MHz,
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.src = SRC_GPLL0_EVEN_300MHZ,
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.div = QCOM_CLOCK_DIV(1),
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.m = 4,
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.n = 25,
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.d_2 = 25,
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},
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{
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.hz = 64 * MHz,
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.src = SRC_GPLL0_EVEN_300MHZ,
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.div = QCOM_CLOCK_DIV(1),
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.m = 16,
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.n = 75,
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.d_2 = 75,
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},
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{
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.hz = 96 * MHz,
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.src = SRC_GPLL0_EVEN_300MHZ,
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.div = QCOM_CLOCK_DIV(1),
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.m = 8,
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.n = 25,
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.d_2 = 25,
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},
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{
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.hz = 100 * MHz,
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.src = SRC_GPLL0_MAIN_600MHZ,
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.div = QCOM_CLOCK_DIV(6),
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},
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};
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void clock_configure_qspi(uint32_t hz)
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{
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/* placeholder */
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clock_configure(&gcc->qspi_core, qspi_core_cfg, hz, ARRAY_SIZE(qspi_core_cfg));
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clock_enable(&gcc->qspi_cnoc_ahb_cbcr);
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clock_enable(&gcc->qspi_core_cbcr);
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}
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void clock_enable_qup(int qup)
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{
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/* placeholder */
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struct qupv3_clock *qup_clk;
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int s = qup % QUP_WRAP1_S0, clk_en_off;
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void *clk_br_en_ptr = NULL; // Pointer to the correct apcs_clk_br_enX
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qup_clk = qup < QUP_WRAP1_S0 ? &gcc->qup_wrap0_s[s] : qup < QUP_WRAP2_S0 ?
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&gcc->qup_wrap1_s[s] : &gcc->qup_wrap2_s[s];
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if (qup <= QUP_WRAP0_S7) {
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clk_en_off = QUPV3_WRAP0_CLK_ENA_S(s);
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clk_br_en_ptr = &gcc->apcs_clk_br_en4;
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} else if (qup >= QUP_WRAP1_S0 && qup <= QUP_WRAP1_S6) {
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clk_en_off = QUPV3_WRAP1_CLK_ENA_S(s);
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clk_br_en_ptr = &gcc->apcs_clk_br_en1;
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} else if (qup >= QUP_WRAP2_S0 && qup <= QUP_WRAP2_S6) {
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clk_en_off = QUPV3_WRAP2_CLK_ENA_S(s);
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clk_br_en_ptr = &gcc->apcs_clk_br_en2;
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} else if (qup == QUP_WRAP1_S7 || qup == QUP_WRAP2_S7) {
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clk_en_off = qup == QUP_WRAP1_S7 ? QUPV3_WRAP1_SE7_CLK_ENA : QUPV3_WRAP2_SE7_CLK_ENA;
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clk_br_en_ptr = &gcc->apcs_clk_br_en2;
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}
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/* Only call if a valid pointer was assigned */
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if (clk_br_en_ptr)
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clock_enable_vote(&qup_clk->cbcr, clk_br_en_ptr, clk_en_off);
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}
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void clock_configure_dfsr(int qup)
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{
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/* placeholder */
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clock_configure_dfsr_table(qup, qupv3_wrap_cfg,
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ARRAY_SIZE(qupv3_wrap_cfg));
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}
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static enum cb_err clock_configure_gpll0(void)
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{
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struct alpha_pll_reg_val_config gpll0_cfg = {0};
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gpll0_cfg.reg_user_ctl = &gcc->gpll0.user_ctl;
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gpll0_cfg.user_ctl_val = (read32(gpll0_cfg.reg_user_ctl) |
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1 << PLL_POST_DIV_EVEN_SHFT_X1P42100 |
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2 << PLL_POST_DIV_ODD_SHFT_X1P42100 |
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1 << PLL_PLLOUT_EVEN_SHFT_X1P42100 |
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1 << PLL_PLLOUT_MAIN_SHFT_X1P42100 |
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1 << PLL_PLLOUT_ODD_SHFT_X1P42100);
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return clock_configure_enable_gpll(&gpll0_cfg, false, 0);
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}
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static void speed_up_boot_cpu(void)
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{
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/* Placeholder */
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}
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void clock_init(void)
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{
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/* placeholder */
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clock_configure_gpll0();
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clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr,
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&gcc->apcs_clk_br_en4,
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QUPV3_WRAP0_CORE_2X_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap0_core_cbcr,
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&gcc->apcs_clk_br_en4,
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QUPV3_WRAP0_CORE_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr,
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&gcc->apcs_clk_br_en4,
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QUPV3_WRAP_0_M_AHB_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr,
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&gcc->apcs_clk_br_en4,
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QUPV3_WRAP_0_S_AHB_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr,
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&gcc->apcs_clk_br_en1,
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QUPV3_WRAP1_CORE_2X_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap1_core_cbcr,
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&gcc->apcs_clk_br_en1,
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QUPV3_WRAP1_CORE_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr,
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&gcc->apcs_clk_br_en1,
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QUPV3_WRAP_1_M_AHB_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr,
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&gcc->apcs_clk_br_en1,
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QUPV3_WRAP_1_S_AHB_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap2_core_2x_cbcr,
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&gcc->apcs_clk_br_en2,
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QUPV3_WRAP2_CORE_2X_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap2_core_cbcr,
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&gcc->apcs_clk_br_en2,
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QUPV3_WRAP2_CORE_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap2_m_ahb_cbcr,
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&gcc->apcs_clk_br_en2,
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QUPV3_WRAP_2_M_AHB_CLK_ENA);
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clock_enable_vote(&gcc->qup_wrap2_s_ahb_cbcr,
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&gcc->apcs_clk_br_en2,
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QUPV3_WRAP_2_S_AHB_CLK_ENA);
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speed_up_boot_cpu();
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}
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@ -8,6 +8,7 @@
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#define AOSS_CC_BASE 0x0C2A0000
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#define QSPI_BASE 0x088DC000
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#define TLMM_TILE_BASE 0x0F100000
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#define GCC_BASE 0x00100000
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/* X1P42100 QSPI GPIO PINS */
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#define QSPI_CS GPIO(132)
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@ -7,7 +7,141 @@
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#ifndef __SOC_QUALCOMM_X1P42100_CLOCK_H__
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#define __SOC_QUALCOMM_X1P42100_CLOCK_H__
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#define SRC_XO_HZ (38400 * KHz)
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#define SRC_XO_HZ (19200 * KHz)
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#define GPLL0_EVEN_HZ (300 * MHz)
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#define GPLL0_MAIN_HZ (600 * MHz)
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#define CLK_100MHZ (100 * MHz)
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#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx)
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#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx)
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#define QUPV3_WRAP2_CLK_ENA_S(idx) (4 + idx)
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#define QUPV3_WRAP1_SE7_CLK_ENA 16
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#define QUPV3_WRAP2_SE7_CLK_ENA 17
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enum clk_ctl_gpll_user_ctl_x1p42100 {
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PLL_PLLOUT_MAIN_SHFT_X1P42100 = 0,
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PLL_PLLOUT_EVEN_SHFT_X1P42100 = 1,
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PLL_PLLOUT_ODD_SHFT_X1P42100 = 2,
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PLL_POST_DIV_EVEN_SHFT_X1P42100 = 10,
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PLL_POST_DIV_ODD_SHFT_X1P42100 = 14,
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};
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enum clk_pll_src {
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SRC_XO_19_2MHZ = 0,
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SRC_GPLL0_MAIN_600MHZ = 1,
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SRC_GPLL9_MAIN_808MHZ = 2,
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SRC_GCC_DISP_GPLL0_CLK = 4,
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SRC_GPLL10_MAIN_384MHZ = 5,
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SRC_GPLL0_EVEN_300MHZ = 6,
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};
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enum apcs_branch_en_vote {
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QUPV3_WRAP_0_M_AHB_CLK_ENA = 6,
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QUPV3_WRAP_0_S_AHB_CLK_ENA = 7,
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QUPV3_WRAP0_CORE_CLK_ENA = 8,
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QUPV3_WRAP0_CORE_2X_CLK_ENA = 9,
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QUPV3_WRAP1_CORE_2X_CLK_ENA = 18,
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QUPV3_WRAP1_CORE_CLK_ENA = 19,
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QUPV3_WRAP_1_M_AHB_CLK_ENA = 20,
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QUPV3_WRAP_1_S_AHB_CLK_ENA = 21,
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QUPV3_WRAP2_CORE_2X_CLK_ENA = 3,
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QUPV3_WRAP2_CORE_CLK_ENA = 0,
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QUPV3_WRAP_2_M_AHB_CLK_ENA = 2,
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QUPV3_WRAP_2_S_AHB_CLK_ENA = 1,
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};
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struct x1p42100_gpll {
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u32 mode;
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u32 opmode;
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u32 state;
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u32 status;
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u32 l;
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u32 alpha;
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u32 user_ctl;
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u32 user_ctl_u;
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u32 config_ctl;
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u32 config_ctl_u;
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u32 config_ctl_u1;
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};
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struct x1p42100_gcc {
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struct x1p42100_gpll gpll0;
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u8 _res1[0x18004 - 0x0002c];
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struct qupv3_clock qup_wrap1_s[8];
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u8 _res2[0x1e004 - 0x189c4];
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struct qupv3_clock qup_wrap2_s[8];
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u8 _res3[0x23000 - 0x1e9c4];
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u32 qup_wrap0_m_ahb_cbcr;
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u32 qup_wrap0_s_ahb_cbcr;
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u32 qup_wrap0_core_cbcr;
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u8 _res4[0x23014 - 0x2300c];
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u32 qup_wrap0_core_cdivr;
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u32 qup_wrap0_core_2x_cbcr;
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u8 _res5[0x23024 - 0x2301c];
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struct clock_rcg qup_wrap0_core_2x;
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u8 _res6[0x23150 - 0x2302c];
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u32 qup_wrap1_m_ahb_cbcr;
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u32 qup_wrap1_s_ahb_cbcr;
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u32 qup_wrap1_core_cbcr;
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u8 _res7[0x23164 - 0x2315c];
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u32 qup_wrap1_core_cdivr;
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u32 qup_wrap1_core_2x_cbcr;
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u8 _res8[0x23174 - 0x2316c];
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struct clock_rcg qup_wrap1_core_2x;
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u8 _res9[0x232a0 - 0x2317c];
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u32 qup_wrap2_m_ahb_cbcr;
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u32 qup_wrap2_s_ahb_cbcr;
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u32 qup_wrap2_core_cbcr;
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u8 _res10[0x232b4 - 0x232ac];
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u32 qup_wrap2_core_cdivr;
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u32 qup_wrap2_core_2x_cbcr;
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u8 _res11[0x232c4 - 0x232bc];
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struct clock_rcg qup_wrap2_core_2x;
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u8 _res12[0x42004 - 0x232cc];
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struct qupv3_clock qup_wrap0_s[8];
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u8 _res13[0x4b000 - 0x429c4];
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u32 qspi_bcr;
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u32 qspi_cnoc_ahb_cbcr;
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u32 qspi_core_cbcr;
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struct clock_rcg qspi_core;
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u8 _res14[0x52000 - 0x4b014];
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u32 apcs_clk_br_en;
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u8 _res15[0x52008 - 0x52004];
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u32 apcs_clk_br_en1;
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u8 _res16[0x52010 - 0x5200C];
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u32 apcs_clk_br_en2;
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u8 _res17[0x52018 - 0x52014];
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u32 apcs_clk_br_en3;
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u8 _res18[0x52020 - 0x5201c];
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u32 apcs_clk_br_en4;
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u8 _res19[0x52028 - 0x52024];
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u32 apcs_clk_br_en5;
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u8 _res20[0x52030 - 0x5202c];
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u32 apcs_pll_br_en;
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};
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check_member(x1p42100_gcc, qup_wrap1_s, 0x18004);
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check_member(x1p42100_gcc, qup_wrap2_s, 0x1e004);
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check_member(x1p42100_gcc, qup_wrap0_m_ahb_cbcr, 0x23000);
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check_member(x1p42100_gcc, qup_wrap0_core_cdivr, 0x23014);
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check_member(x1p42100_gcc, qup_wrap0_core_2x, 0x23024);
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check_member(x1p42100_gcc, qup_wrap1_m_ahb_cbcr, 0x23150);
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check_member(x1p42100_gcc, qup_wrap1_core_cdivr, 0x23164);
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check_member(x1p42100_gcc, qup_wrap1_core_2x, 0x23174);
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check_member(x1p42100_gcc, qup_wrap2_m_ahb_cbcr, 0x232a0);
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check_member(x1p42100_gcc, qup_wrap2_core_cdivr, 0x232b4);
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check_member(x1p42100_gcc, qup_wrap2_core_2x, 0x232c4);
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check_member(x1p42100_gcc, qup_wrap0_s, 0x42004);
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check_member(x1p42100_gcc, qspi_bcr, 0x4b000);
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check_member(x1p42100_gcc, apcs_clk_br_en, 0x52000);
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check_member(x1p42100_gcc, apcs_clk_br_en1, 0x52008);
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check_member(x1p42100_gcc, apcs_clk_br_en2, 0x52010);
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check_member(x1p42100_gcc, apcs_clk_br_en3, 0x52018);
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check_member(x1p42100_gcc, apcs_clk_br_en4, 0x52020);
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check_member(x1p42100_gcc, apcs_clk_br_en5, 0x52028);
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check_member(x1p42100_gcc, apcs_pll_br_en, 0x52030);
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enum clk_qup {
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QUP_WRAP0_S0,
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@ -44,5 +178,6 @@ void clock_configure_dfsr(int qup);
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/* Subsystem Reset */
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static struct aoss *const aoss = (void *)AOSS_CC_BASE;
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static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
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#endif // __SOC_QUALCOMM_X1P42100_CLOCK_H__
|
||||
|
|
|
|||
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